Commit 91bcbc11 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-renesas', 'clk-rockchip', 'clk-const' and 'clk-simplify' into clk-next 

* clk-renesas:
  clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain
  clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
  clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain
  dt-bindings: clk: emev2: Rename bindings documentation file
  clk: renesas: rcar-usb2-clock-sel: Use devm_platform_ioremap_resource() helper

* clk-rockchip:
  clk: rockchip: Add clock controller for the rk3308
  clk: rockchip: Add dt-binding header for rk3308
  dt-bindings: Add bindings for rk3308 clock controller
  clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver

* clk-const:
  clk: spear: Make structure i2s_sclk_masks constant

* clk-simplify:
  clk/ti: Use kmemdup rather than duplicating its implementation
  clk: fix devm_platform_ioremap_resource.cocci warnings
parents a1ff1ce3 339bc7c0 af8fc26f f5c009db 81b94f14

Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt

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* Rockchip RK3308 Clock and Reset Unit



The RK3308 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: CRU should be "rockchip,rk3308-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing, pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",

   "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",

   "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,

 - "mac_clkin" - external MAC clock - optional



Example: Clock controller node:



	cru: clock-controller@ff500000 {

		compatible = "rockchip,rk3308-cru";

		reg = <0x0 0xff500000 0x0 0x1000>;

		rockchip,grf = <&grf>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@ff0a0000 {

		compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";

		reg = <0x0 0xff0a0000 0x0 0x100>;

		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;

		clock-names = "baudclk", "apb_pclk";

		reg-shift = <2>;

		reg-io-width = <4>;

		status = "disabled";

	};

drivers/clk/bcm/clk-bcm63xx-gate.c

+1 −3
Original line number Diff line number Diff line
@@ -146,7 +146,6 @@ static int clk_bcm63xx_probe(struct platform_device *pdev) 
{

	const struct clk_bcm63xx_table_entry *entry, *table;

	struct clk_bcm63xx_hw *hw;

	struct resource *r;

	u8 maxbit = 0;

	int i, ret;
@@ -170,8 +169,7 @@ static int clk_bcm63xx_probe(struct platform_device *pdev) 
	for (i = 0; i < maxbit; i++)

		hw->data.hws[i] = ERR_PTR(-ENODEV);



	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	hw->regs = devm_ioremap_resource(&pdev->dev, r);

	hw->regs = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(hw->regs))

		return PTR_ERR(hw->regs);

drivers/clk/renesas/clk-mstp.c

+2 −1
Original line number Diff line number Diff line
@@ -334,7 +334,8 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np) 
		return;



	pd->name = np->name;

	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;

	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |

		    GENPD_FLAG_ACTIVE_WAKEUP;

	pd->attach_dev = cpg_mstp_attach_dev;

	pd->detach_dev = cpg_mstp_detach_dev;

	pm_genpd_init(pd, &pm_domain_always_on_gov, false);

drivers/clk/renesas/r9a06g032-clocks.c

+2 −1
Original line number Diff line number Diff line
@@ -421,7 +421,8 @@ static int r9a06g032_add_clk_domain(struct device *dev) 
		return -ENOMEM;



	pd->name = np->name;

	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;

	pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |

		    GENPD_FLAG_ACTIVE_WAKEUP;

	pd->attach_dev = r9a06g032_attach_dev;

	pd->detach_dev = r9a06g032_detach_dev;

	pm_genpd_init(pd, &pm_domain_always_on_gov, false);

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