Commit a1ff1ce3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into clk-next

 - Set clk_init_data pointer inside clk_hw to NULL after registration

* clk-init-destroy:
  clk: Overwrite clk_hw::init with NULL during clk_register()
  clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
  clk: ti: Don't reference clk_init_data after registration
  clk: qcom: Remove error prints from DFS registration
  rtc: sun6i: Don't reference clk_init_data after registration
  clk: zx296718: Don't reference clk_init_data after registration
  clk: milbeaut: Don't reference clk_init_data after registration
  clk: socfpga: deindent code to proper indentation
  phy: ti: am654-serdes: Don't reference clk_init_data after registration
  clk: sprd: Don't reference clk_init_data after registration
  clk: socfpga: Don't reference clk_init_data after registration
  clk: sirf: Don't reference clk_init_data after registration
  clk: qcom: Don't reference clk_init_data after registration
  clk: meson: axg-audio: Don't reference clk_init_data after registration
  clk: lochnagar: Don't reference clk_init_data after registration
  clk: actions: Don't reference clk_init_data after registration

* clk-doc:
  clk: remove extra ---help--- tags in Kconfig
  clk: add include guard to clk-conf.h
  clk: Document of_parse_clkspec() some more
  clk: Remove extraneous 'for' word in comments

* clk-imx: (32 commits)
  clk: imx: imx8mn: fix pll mux bit
  clk: imx: imx8mm: fix pll mux bit
  clk: imx: clk-pll14xx: unbypass PLL by default
  clk: imx: pll14xx: avoid glitch when set rate
  clk: imx: imx8mn: fix audio pll setting
  clk: imx8mn: Add necessary frequency support for ARM PLL table
  clk: imx8mn: Add missing rate_count assignment for each PLL structure
  clk: imx8mn: fix int pll clk gate
  clk: imx8mn: Add GIC clock
  clk: imx8mn: Fix incorrect parents
  clk: imx8mm: Fix incorrect parents
  clk: imx8mq: Fix sys3 pll references
  clk: imx8mq: Unregister clks when of_clk_add_provider failed
  clk: imx8mm: Unregister clks when of_clk_add_provider failed
  clk: imx8mq: Mark AHB clock as critical
  clk: imx8mn: Keep uart clocks on for early console
  clk: imx: Remove unused function statement
  clk: imx7ulp: Make sure earlycon's clock is enabled
  clk: imx8mm: Switch to platform driver
  clk: imx: imx8mm: fix audio pll setting
  ...

* clk-allwinner:
  clk: sunxi-ng: h6: Allow I2S to change parent rate
  clk: sunxi-ng: v3s: add Allwinner V3 support
  clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
  dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
  clk: sunxi-ng: v3s: add the missing PLL_DDR1
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+1 −0
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@@ -31,6 +31,7 @@ properties:
      - allwinner,sun8i-h3-ccu
      - allwinner,sun8i-h3-r-ccu
      - allwinner,sun8i-r40-ccu
      - allwinner,sun8i-v3-ccu
      - allwinner,sun8i-v3s-ccu
      - allwinner,sun9i-a80-ccu
      - allwinner,sun50i-a64-ccu
+112 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8M Nano Clock Control Module Binding

maintainers:
  - Anson Huang <Anson.Huang@nxp.com>

description: |
  NXP i.MX8M Nano clock control module is an integrated clock controller, which
  generates and supplies to all modules.

properties:
  compatible:
    const: fsl,imx8mn-ccm

  reg:
    maxItems: 1

  clocks:
    items:
      - description: 32k osc
      - description: 24m osc
      - description: ext1 clock input
      - description: ext2 clock input
      - description: ext3 clock input
      - description: ext4 clock input

  clock-names:
    items:
      - const: osc_32k
      - const: osc_24m
      - const: clk_ext1
      - const: clk_ext2
      - const: clk_ext3
      - const: clk_ext4

  '#clock-cells':
    const: 1
    description: |
      The clock consumer should specify the desired clock by having the clock
      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
      for the full list of i.MX8M Nano clock IDs.

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

examples:
  # Clock Control Module node:
  - |
    clk: clock-controller@30380000 {
        compatible = "fsl,imx8mn-ccm";
        reg = <0x0 0x30380000 0x0 0x10000>;
        #clock-cells = <1>;
        clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
                 <&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
        clock-names = "osc_32k", "osc_24m", "clk_ext1",
                      "clk_ext2", "clk_ext3", "clk_ext4";
    };

  # Required external clocks for Clock Control Module node:
  - |
    osc_32k: clock-osc-32k {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <32768>;
        clock-output-names = "osc_32k";
    };

    osc_24m: clock-osc-24m {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <24000000>;
        clock-output-names = "osc_24m";
    };

    clk_ext1: clock-ext1 {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <133000000>;
        clock-output-names = "clk_ext1";
    };

    clk_ext2: clock-ext2 {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <133000000>;
        clock-output-names = "clk_ext2";
    };

    clk_ext3: clock-ext3 {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <133000000>;
        clock-output-names = "clk_ext3";
    };

    clk_ext4: clock-ext4 {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency= <133000000>;
        clock-output-names = "clk_ext4";
    };

...
+0 −9
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@@ -116,7 +116,6 @@ config COMMON_CLK_SI514
	depends on OF
	select REGMAP_I2C
	help
	---help---
	  This driver supports the Silicon Labs 514 programmable clock
	  generator.

@@ -125,7 +124,6 @@ config COMMON_CLK_SI544
	depends on I2C
	select REGMAP_I2C
	help
	---help---
	  This driver supports the Silicon Labs 544 programmable clock
	  generator.

@@ -135,7 +133,6 @@ config COMMON_CLK_SI570
	depends on OF
	select REGMAP_I2C
	help
	---help---
	  This driver supports Silicon Labs 570/571/598/599 programmable
	  clock generators.

@@ -153,7 +150,6 @@ config COMMON_CLK_CDCE925
	depends on OF
	select REGMAP_I2C
	help
	---help---
	  This driver supports the TI CDCE913/925/937/949 programmable clock
	  synthesizer. Each chip has different number of PLLs and outputs.
	  For example, the CDCE925 contains two PLLs with spread-spectrum
@@ -212,7 +208,6 @@ config COMMON_CLK_AXI_CLKGEN
	tristate "AXI clkgen driver"
	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
	help
	---help---
	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
	  FPGAs. It is commonly used in Analog Devices' reference designs.

@@ -279,26 +274,22 @@ config COMMON_CLK_VC5
	depends on OF
	select REGMAP_I2C
	help
	---help---
	  This driver supports the IDT VersaClock 5 and VersaClock 6
	  programmable clock generators.

config COMMON_CLK_STM32MP157
	def_bool COMMON_CLK && MACH_STM32MP157
	help
	---help---
	  Support for stm32mp157 SoC family clocks

config COMMON_CLK_STM32F
	def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
	help
	---help---
	  Support for stm32f4 and stm32f7 SoC families clocks

config COMMON_CLK_STM32H7
	def_bool COMMON_CLK && MACH_STM32H743
	help
	---help---
	  Support for stm32h7 SoC family clocks

config COMMON_CLK_BD718XX
+3 −2
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@@ -68,16 +68,17 @@ int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
	struct clk_hw *hw;

	for (i = 0; i < hw_clks->num; i++) {
		const char *name;

		hw = hw_clks->hws[i];

		if (IS_ERR_OR_NULL(hw))
			continue;

		name = hw->init->name;
		ret = devm_clk_hw_register(dev, hw);
		if (ret) {
			dev_err(dev, "Couldn't register clock %d - %s\n",
				i, hw->init->name);
				i, name);
			return ret;
		}
	}
+1 −1
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@@ -198,7 +198,7 @@ static u8 lochnagar_clk_get_parent(struct clk_hw *hw)
	if (ret < 0) {
		dev_dbg(priv->dev, "Failed to read parent of %s: %d\n",
			lclk->name, ret);
		return hw->init->num_parents;
		return clk_hw_get_num_parents(hw);
	}

	val &= lclk->src_mask;
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