Merge tag 'v5.4-rockchip-clk1' of...

* Rockchip RK3308 Clock and Reset Unit

The RK3308 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.

Required Properties:

- compatible: CRU should be "rockchip,rk3308-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.

Optional Properties:

- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing, pll rates are not changeable, due to the missing pll lock status.

Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.

External clocks:

There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "xin32k" - rtc clock - optional,

 - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",

   "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in",

   "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional,

 - "mac_clkin" - external MAC clock - optional

Example: Clock controller node:

	cru: clock-controller@ff500000 {

		compatible = "rockchip,rk3308-cru";

		reg = <0x0 0xff500000 0x0 0x1000>;

		rockchip,grf = <&grf>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

Example: UART controller node that consumes the clock generated by the clock

  controller:

	uart0: serial@ff0a0000 {

		compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";

		reg = <0x0 0xff0a0000 0x0 0x100>;

		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;

		clock-names = "baudclk", "apb_pclk";

		reg-shift = <2>;

		reg-io-width = <4>;

		status = "disabled";

	};

obj-y	+= clk-rk3188.o

obj-y	+= clk-rk3228.o

obj-y	+= clk-rk3288.o

obj-y	+= clk-rk3308.o

obj-y	+= clk-rk3328.o

obj-y	+= clk-rk3368.o

obj-y	+= clk-rk3399.o

PNAME(mux_hdmiphy_phy_p)	= { "hdmiphy", "xin24m" };

PNAME(mux_dclk_hdmiphy_pre_p)	= { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };

PNAME(mux_pll_src_4plls_p)	= { "dpll", "gpll", "hdmiphy", "usb480m" };

PNAME(mux_pll_src_3plls_p)	= { "apll", "gpll", "dpll" };

PNAME(mux_pll_src_2plls_p)	= { "dpll", "gpll" };

PNAME(mux_pll_src_apll_gpll_p)	= { "apll", "gpll" };

PNAME(mux_aclk_peri_src_p)	= { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };

#define RK3288_EMMC_CON0		0x218

#define RK3288_EMMC_CON1		0x21c

#define RK3308_PLL_CON(x)		RK2928_PLL_CON(x)

#define RK3308_CLKSEL_CON(x)		((x) * 0x4 + 0x100)

#define RK3308_CLKGATE_CON(x)		((x) * 0x4 + 0x300)

#define RK3308_GLB_SRST_FST		0xb8

#define RK3308_SOFTRST_CON(x)		((x) * 0x4 + 0x400)

#define RK3308_MODE_CON			0xa0

#define RK3308_SDMMC_CON0		0x480

#define RK3308_SDMMC_CON1		0x484

#define RK3308_SDIO_CON0		0x488

#define RK3308_SDIO_CON1		0x48c

#define RK3308_EMMC_CON0		0x490

#define RK3308_EMMC_CON1		0x494

#define RK3328_PLL_CON(x)		RK2928_PLL_CON(x)

#define RK3328_CLKSEL_CON(x)		((x) * 0x4 + 0x100)

#define RK3328_CLKGATE_CON(x)		((x) * 0x4 + 0x200)