Commit ac68dfd3 authored by Finley Xiao's avatar Finley Xiao Committed by Heiko Stuebner
Browse files

clk: rockchip: Add clock controller for the rk3308 



Add the clock tree definition for the new RK3308 SoC.

Signed-off-by: default avatarFinley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent efb7740f

drivers/clk/rockchip/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ obj-y += clk-rk3128.o 
obj-y	+= clk-rk3188.o

obj-y	+= clk-rk3228.o

obj-y	+= clk-rk3288.o

obj-y	+= clk-rk3308.o

obj-y	+= clk-rk3328.o

obj-y	+= clk-rk3368.o

obj-y	+= clk-rk3399.o

drivers/clk/rockchip/clk-rk3308.c

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+955 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/rockchip/clk.h

+13 −0
Original line number Diff line number Diff line
@@ -121,6 +121,19 @@ struct clk; 
#define RK3288_EMMC_CON0		0x218

#define RK3288_EMMC_CON1		0x21c



#define RK3308_PLL_CON(x)		RK2928_PLL_CON(x)

#define RK3308_CLKSEL_CON(x)		((x) * 0x4 + 0x100)

#define RK3308_CLKGATE_CON(x)		((x) * 0x4 + 0x300)

#define RK3308_GLB_SRST_FST		0xb8

#define RK3308_SOFTRST_CON(x)		((x) * 0x4 + 0x400)

#define RK3308_MODE_CON			0xa0

#define RK3308_SDMMC_CON0		0x480

#define RK3308_SDMMC_CON1		0x484

#define RK3308_SDIO_CON0		0x488

#define RK3308_SDIO_CON1		0x48c

#define RK3308_EMMC_CON0		0x490

#define RK3308_EMMC_CON1		0x494



#define RK3328_PLL_CON(x)		RK2928_PLL_CON(x)

#define RK3328_CLKSEL_CON(x)		((x) * 0x4 + 0x100)

#define RK3328_CLKGATE_CON(x)		((x) * 0x4 + 0x200)

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