Commit 74ca9288 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'clk-imx' into clk-next 

* clk-hisi:
  clk: hi6220: use CLK_OF_DECLARE_DRIVER

* clk-amlogic:
  clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
  clk: meson: axg_audio: add sm1 support
  clk: meson: axg-audio: provide clk top signal name
  clk: meson: axg-audio: prepare sm1 addition
  clk: meson: axg-audio: fix regmap last register
  clk: meson: axg-audio: remove useless defines
  dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
  dt-bindings: clk: axg-audio: add sm1 bindings
  clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
  clk: meson: g12a: fix cpu clock rate setting
  clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate

* clk-samsung:
  clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path
  clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume
  clk: samsung: exynos5420: Add VPLL rate table
  clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
  clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
  clk: samsung: exynos5433: Fix error paths

* clk-renesas: (23 commits)
  clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
  clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
  dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
  clk: renesas: r8a77965: Remove superfluous semicolon
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example
  dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions
  clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
  clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()
  clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
  clk: renesas: r8a774b1: Add TMU clock
  clk: renesas: cpg-mssr: Add r8a774b1 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding
  clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
  clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
  clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
  clk: renesas: rcar-gen3: Improve arithmetic divisions
  clk: renesas: rcar-gen2: Improve arithmetic divisions
  clk: renesas: Remove R-Car Gen2 legacy DT clock support
  ...

* clk-imx:
  clk: imx: imx8mq: fix sys3_pll_out_sels
  clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock
  clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code
  clk: imx7ulp: Correct DDR clock mux options
  clk: imx7ulp: Correct system clock source option #7
  clk: imx: imx8mq: mark sys1/2_pll as fixed clock
  clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
  clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
  clk: imx8mn: Define gates for pll1/2 fixed dividers
  clk: imx8mm: Define gates for pll1/2 fixed dividers
  clk: imx8mq: Define gates for pll1/2 fixed dividers
  clk: imx: clk-pll14xx: Make two variables static
  clk: imx8mq: Add VIDEO2_PLL clock
  clk: imx8mn: Use common 1443X/1416X PLL clock structure
  clk: imx8mm: Move 1443X/1416X PLL clock structure to common place
  clk: imx: pll14xx: Fix quick switch of S/K parameter
parents 13032310 f1edb498 fac3810f 60632440 b7c1b40a bfd582aa

Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

+2 −1
Original line number Original line Diff line number Diff line
@@ -7,7 +7,8 @@ devices. 
Required Properties:

Required Properties:





- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,

- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,

		  "amlogic,g12a-audio-clkc" for G12A.

		  "amlogic,g12a-audio-clkc" for G12A,

		  "amlogic,sm1-audio-clkc" for S905X3.

- reg		: physical base address of the clock controller and length of

- reg		: physical base address of the clock controller and length of

		  memory mapped region.

		  memory mapped region.

- clocks	: a list of phandle + clock-specifier pairs for the clocks listed

- clocks	: a list of phandle + clock-specifier pairs for the clocks listed

Documentation/devicetree/bindings/clock/imx7ulp-clock.txt

+0 −1
Original line number Original line Diff line number Diff line
@@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 { 
		 <&scg1 IMX7ULP_CLK_APLL_PFD0>,

		 <&scg1 IMX7ULP_CLK_APLL_PFD0>,

		 <&scg1 IMX7ULP_CLK_UPLL>,

		 <&scg1 IMX7ULP_CLK_UPLL>,

		 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_MIPI_PLL>,

		 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,

		 <&scg1 IMX7ULP_CLK_ROSC>,

		 <&scg1 IMX7ULP_CLK_ROSC>,

		 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

		 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+8 −5
Original line number Original line Diff line number Diff line
@@ -19,6 +19,7 @@ Required Properties: 
      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
@@ -26,7 +27,8 @@ Required Properties: 
      - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)

      - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)

      - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)

      - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)

      - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)

      - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)

      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)

      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)

      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)

      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)

      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)

      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
@@ -40,10 +42,11 @@ Required Properties: 
    clock-names

    clock-names

  - clock-names: List of external parent clock names. Valid names are:

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,

      - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,

		 r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,

		 r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,

		 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,

		 r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,

		 r8a77995)

		 r8a77980, r8a77990, r8a77995)

      - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)

      - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,

		  r8a77970, r8a77980)

      - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,

      - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,

		     r8a7793, r8a7794)

		     r8a7793, r8a7794)

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

deleted100644 → 0
+0 −60
Original line number Original line Diff line number Diff line 
* Renesas R-Car Gen2 Clock Pulse Generator (CPG)



The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs

and several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.



Required Properties:



  - compatible: Must be one of

    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG

    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG

    - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG

    - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG

    - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG

    and "renesas,rcar-gen2-cpg-clocks" as a fallback.



  - reg: Base address and length of the memory resource used by the CPG



  - clocks: References to the parent clocks: first to the EXTAL clock, second

    to the USB_EXTAL clock

  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are "main",

    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and

    "adsp"

  - #power-domain-cells: Must be 0



SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed

through an MSTP clock should refer to the CPG device node in their

"power-domains" property, as documented by the generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.





Examples

--------



  - CPG device node:



	cpg_clocks: cpg_clocks@e6150000 {

		compatible = "renesas,r8a7790-cpg-clocks",

			     "renesas,rcar-gen2-cpg-clocks";

		reg = <0 0xe6150000 0 0x1000>;

		clocks = <&extal_clk &usb_extal_clk>;

		#clock-cells = <1>;

		clock-output-names = "main", "pll0, "pll1", "pll3",

				     "lb", "qspi", "sdh", "sd0", "sd1", "z",

				     "rcan", "adsp";

		#power-domain-cells = <0>;

	};





  - CPG/MSTP Clock Domain member device node:



	thermal@e61f0000 {

		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";

		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;

		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;

		power-domains = <&cpg_clocks>;

	};

Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt

+1 −1
Original line number Original line Diff line number Diff line
@@ -46,7 +46,7 @@ Required properties: 
Example (R-Car H3):

Example (R-Car H3):





	usb2_clksel: clock-controller@e6590630 {

	usb2_clksel: clock-controller@e6590630 {

		compatible = "renesas,r8a77950-rcar-usb2-clock-sel",

		compatible = "renesas,r8a7795-rcar-usb2-clock-sel",

			     "renesas,rcar-gen3-usb2-clock-sel";

			     "renesas,rcar-gen3-usb2-clock-sel";

		reg = <0 0xe6590630 0 0x02>;

		reg = <0 0xe6590630 0 0x02>;

		clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;

		clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE