Commit b7c1b40a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.5-tag2' of... 

Merge tag 'clk-renesas-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Switch some clocks on R-Car Gen2/3 to .determine_rate()
 - Add support for the new R-Car M3-W+ (r8a77961) SoC
 - Add support for the new RZ/G2N (r8a774b1) SoC
 - Remove R-Car Gen2 legacy DT clock support
 - Improve arithmetic divisions on R-Car Gen2 and Gen3
 - Improve R-Car Gen3 SD clock handling

* tag 'clk-renesas-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (23 commits)
  clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support
  clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960
  dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support
  clk: renesas: r8a77965: Remove superfluous semicolon
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example
  dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions
  clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
  clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()
  clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
  clk: renesas: r8a774b1: Add TMU clock
  clk: renesas: cpg-mssr: Add r8a774b1 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding
  clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
  clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
  clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
  clk: renesas: rcar-gen3: Improve arithmetic divisions
  clk: renesas: rcar-gen2: Improve arithmetic divisions
  clk: renesas: Remove R-Car Gen2 legacy DT clock support
  ...
parents 54ecb8f7 2ba738d5

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+8 −5
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ Required Properties: 
      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
@@ -26,7 +27,8 @@ Required Properties: 
      - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)

      - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)

      - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)

      - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)

      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)

      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)

      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
@@ -40,10 +42,11 @@ Required Properties: 
    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,

		 r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,

		 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,

		 r8a77995)

      - "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)

		 r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,

		 r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,

		 r8a77980, r8a77990, r8a77995)

      - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,

		  r8a77970, r8a77980)

      - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,

		     r8a7793, r8a7794)

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

deleted100644 → 0
+0 −60
Original line number Diff line number Diff line 
* Renesas R-Car Gen2 Clock Pulse Generator (CPG)



The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs

and several fixed ratio dividers.

The CPG also provides a Clock Domain for SoC devices, in combination with the

CPG Module Stop (MSTP) Clocks.



Required Properties:



  - compatible: Must be one of

    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG

    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG

    - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG

    - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG

    - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG

    and "renesas,rcar-gen2-cpg-clocks" as a fallback.



  - reg: Base address and length of the memory resource used by the CPG



  - clocks: References to the parent clocks: first to the EXTAL clock, second

    to the USB_EXTAL clock

  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are "main",

    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and

    "adsp"

  - #power-domain-cells: Must be 0



SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed

through an MSTP clock should refer to the CPG device node in their

"power-domains" property, as documented by the generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.





Examples

--------



  - CPG device node:



	cpg_clocks: cpg_clocks@e6150000 {

		compatible = "renesas,r8a7790-cpg-clocks",

			     "renesas,rcar-gen2-cpg-clocks";

		reg = <0 0xe6150000 0 0x1000>;

		clocks = <&extal_clk &usb_extal_clk>;

		#clock-cells = <1>;

		clock-output-names = "main", "pll0, "pll1", "pll3",

				     "lb", "qspi", "sdh", "sd0", "sd1", "z",

				     "rcan", "adsp";

		#power-domain-cells = <0>;

	};





  - CPG/MSTP Clock Domain member device node:



	thermal@e61f0000 {

		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";

		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;

		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;

		power-domains = <&cpg_clocks>;

	};

Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ Required properties: 
Example (R-Car H3):



	usb2_clksel: clock-controller@e6590630 {

		compatible = "renesas,r8a77950-rcar-usb2-clock-sel",

		compatible = "renesas,r8a7795-rcar-usb2-clock-sel",

			     "renesas,rcar-gen3-usb2-clock-sel";

		reg = <0 0xe6590630 0 0x02>;

		clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;

drivers/clk/renesas/Kconfig

+12 −22
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ config CLK_RENESAS 
	select CLK_R8A7745 if ARCH_R8A7745

	select CLK_R8A77470 if ARCH_R8A77470

	select CLK_R8A774A1 if ARCH_R8A774A1

	select CLK_R8A774B1 if ARCH_R8A774B1

	select CLK_R8A774C0 if ARCH_R8A774C0

	select CLK_R8A7778 if ARCH_R8A7778

	select CLK_R8A7779 if ARCH_R8A7779
@@ -20,7 +21,8 @@ config CLK_RENESAS 
	select CLK_R8A7792 if ARCH_R8A7792

	select CLK_R8A7794 if ARCH_R8A7794

	select CLK_R8A7795 if ARCH_R8A7795

	select CLK_R8A7796 if ARCH_R8A7796

	select CLK_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796

	select CLK_R8A77961 if ARCH_R8A77961

	select CLK_R8A77965 if ARCH_R8A77965

	select CLK_R8A77970 if ARCH_R8A77970

	select CLK_R8A77980 if ARCH_R8A77980
@@ -31,17 +33,6 @@ config CLK_RENESAS 


if CLK_RENESAS



config CLK_RENESAS_LEGACY

	bool "Legacy DT clock support"

	depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794

	help

	  Enable backward compatibility with old device trees describing a

	  hierarchical representation of the various CPG and MSTP clocks.



	  Say Y if you want your kernel to work with old DTBs.

	  It is safe to say N if you use the DTS that is supplied with the

	  current kernel source tree.



# SoC

config CLK_EMEV2

	bool "Emma Mobile EV2 clock support" if COMPILE_TEST
@@ -80,6 +71,10 @@ config CLK_R8A774A1 
	bool "RZ/G2M clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A774B1

	bool "RZ/G2N clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A774C0

	bool "RZ/G2E clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG
@@ -94,24 +89,20 @@ config CLK_R8A7779 


config CLK_R8A7790

	bool "R-Car H2 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY

	select CLK_RCAR_GEN2_CPG

	select CLK_RENESAS_DIV6



config CLK_R8A7791

	bool "R-Car M2-W/N clock support" if COMPILE_TEST

	select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY

	select CLK_RCAR_GEN2_CPG

	select CLK_RENESAS_DIV6



config CLK_R8A7792

	bool "R-Car V2H clock support" if COMPILE_TEST

	select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY

	select CLK_RCAR_GEN2_CPG



config CLK_R8A7794

	bool "R-Car E2 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY

	select CLK_RCAR_GEN2_CPG

	select CLK_RENESAS_DIV6
@@ -119,10 +110,14 @@ config CLK_R8A7795 
	bool "R-Car H3 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A7796

config CLK_R8A77960

	bool "R-Car M3-W clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A77961

	bool "R-Car M3-W+ clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A77965

	bool "R-Car M3-N clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG
@@ -155,11 +150,6 @@ config CLK_SH73A0 




# Family

config CLK_RCAR_GEN2

	bool "R-Car Gen2 legacy clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP

	select CLK_RENESAS_DIV6



config CLK_RCAR_GEN2_CPG

	bool "R-Car Gen2 CPG clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSSR

drivers/clk/renesas/Makefile

+3 −2
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A7745)		+= r8a7745-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77470)		+= r8a77470-cpg-mssr.o

obj-$(CONFIG_CLK_R8A774A1)		+= r8a774a1-cpg-mssr.o

obj-$(CONFIG_CLK_R8A774B1)		+= r8a774b1-cpg-mssr.o

obj-$(CONFIG_CLK_R8A774C0)		+= r8a774c0-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7778)		+= clk-r8a7778.o

obj-$(CONFIG_CLK_R8A7779)		+= clk-r8a7779.o
@@ -17,7 +18,8 @@ obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A7792)		+= r8a7792-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7794)		+= r8a7794-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7795)		+= r8a7795-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7796)		+= r8a7796-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77960)		+= r8a7796-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77961)		+= r8a7796-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77965)		+= r8a77965-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77970)		+= r8a77970-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o
@@ -27,7 +29,6 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o 
obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o



# Family

obj-$(CONFIG_CLK_RCAR_GEN2)		+= clk-rcar-gen2.o

obj-$(CONFIG_CLK_RCAR_GEN2_CPG)		+= rcar-gen2-cpg.o

obj-$(CONFIG_CLK_RCAR_GEN3_CPG)		+= rcar-gen3-cpg.o

obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL)	+= rcar-usb2-clock-sel.o

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