Commit fac3810f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v5.5-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk updates from Jerome Brunet:

 - Add sm1 support in the Amlogic audio clock controller

* tag 'clk-meson-v5.5-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
  clk: meson: axg_audio: add sm1 support
  clk: meson: axg-audio: provide clk top signal name
  clk: meson: axg-audio: prepare sm1 addition
  clk: meson: axg-audio: fix regmap last register
  clk: meson: axg-audio: remove useless defines
  dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
  dt-bindings: clk: axg-audio: add sm1 bindings
  clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
  clk: meson: g12a: fix cpu clock rate setting
  clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
parents 54ecb8f7 50bf025b

Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

+2 −1
Original line number Diff line number Diff line
@@ -7,7 +7,8 @@ devices. 
Required Properties:



- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,

		  "amlogic,g12a-audio-clkc" for G12A.

		  "amlogic,g12a-audio-clkc" for G12A,

		  "amlogic,sm1-audio-clkc" for S905X3.

- reg		: physical base address of the clock controller and length of

		  memory mapped region.

- clocks	: a list of phandle + clock-specifier pairs for the clocks listed

drivers/clk/meson/axg-audio.c

+1327 −698

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/meson/axg-audio.h

+20 −1
Original line number Diff line number Diff line
@@ -50,6 +50,20 @@ 
#define AUDIO_CLK_PDMIN_CTRL1	0x0B0

#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4



/* SM1 introduce new register and some shifts :( */

#define AUDIO_CLK_GATE_EN1	0x004

#define AUDIO_SM1_MCLK_A_CTRL	0x008

#define AUDIO_SM1_MCLK_B_CTRL	0x00C

#define AUDIO_SM1_MCLK_C_CTRL	0x010

#define AUDIO_SM1_MCLK_D_CTRL	0x014

#define AUDIO_SM1_MCLK_E_CTRL	0x018

#define AUDIO_SM1_MCLK_F_CTRL	0x01C

#define AUDIO_SM1_MST_PAD_CTRL0	0x020

#define AUDIO_SM1_MST_PAD_CTRL1	0x024

#define AUDIO_SM1_SW_RESET0	0x028

#define AUDIO_SM1_SW_RESET1	0x02C

#define AUDIO_CLK81_CTRL	0x030

#define AUDIO_CLK81_EN		0x034

/*

 * CLKID index values

 * These indices are entirely contrived and do not map onto the hardware.
@@ -115,10 +129,15 @@ 
#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN	150

#define AUD_CLKID_SPDIFOUT_B_CLK_SEL	153

#define AUD_CLKID_SPDIFOUT_B_CLK_DIV	154

#define AUD_CLKID_CLK81_EN		173

#define AUD_CLKID_SYSCLK_A_DIV		174

#define AUD_CLKID_SYSCLK_B_DIV		175

#define AUD_CLKID_SYSCLK_A_EN		176

#define AUD_CLKID_SYSCLK_B_EN		177



/* include the CLKIDs which are part of the DT bindings */

#include <dt-bindings/clock/axg-audio-clkc.h>



#define NR_CLKS	163

#define NR_CLKS	178



#endif /*__AXG_AUDIO_CLKC_H */

drivers/clk/meson/g12a.c

+11 −2
Original line number Diff line number Diff line
@@ -343,6 +343,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x3,

		.shift = 0,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_dyn0_sel",
@@ -353,8 +354,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = { 
			{ .hw = &g12a_fclk_div3.hw },

		},

		.num_parents = 3,

		/* This sub-tree is used a parking clock */

		.flags = CLK_SET_RATE_NO_REPARENT,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -410,6 +410,7 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 2,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_dyn0",
@@ -466,6 +467,7 @@ static struct clk_regmap g12a_cpu_clk_dyn = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 10,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk_dyn",
@@ -485,6 +487,7 @@ static struct clk_regmap g12a_cpu_clk = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 11,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk",
@@ -504,6 +507,7 @@ static struct clk_regmap g12b_cpu_clk = { 
		.offset = HHI_SYS_CPU_CLK_CNTL0,

		.mask = 0x1,

		.shift = 11,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpu_clk",
@@ -523,6 +527,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x3,

		.shift = 0,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk_dyn0_sel",
@@ -533,6 +538,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = { 
			{ .hw = &g12a_fclk_div3.hw },

		},

		.num_parents = 3,

		.flags = CLK_SET_RATE_PARENT,

	},

};
@@ -567,6 +573,7 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x1,

		.shift = 2,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk_dyn0",
@@ -644,6 +651,7 @@ static struct clk_regmap g12b_cpub_clk_dyn = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x1,

		.shift = 10,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk_dyn",
@@ -663,6 +671,7 @@ static struct clk_regmap g12b_cpub_clk = { 
		.offset = HHI_SYS_CPUB_CLK_CNTL,

		.mask = 0x1,

		.shift = 11,

		.flags = CLK_MUX_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "cpub_clk",

drivers/clk/meson/gxbb.c

+1 −0
Original line number Diff line number Diff line
@@ -935,6 +935,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = { 
			&gxbb_sar_adc_clk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};

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