Commit 23cae54f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas'... 

Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas' and 'clk-samsung' into clk-next

 - Camera clks on Qualcomm SC7180 SoCs
 - GCC and RPMh clks on Qualcomm SDX55 SoCs
 - RPMh clks on Qualcomm SM8350 SoCs
 - LPASS clks on Qualcomm SM8250 SoCs
 - Add devm variant of clk_notifier_register()
 - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw

* clk-doc:
  clk: fix a kernel-doc markup

* clk-qcom: (27 commits)
  clk: qcom: rpmh: add support for SM8350 rpmh clocks
  dt-bindings: clock: Add RPMHCC bindings for SM8350
  clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
  clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
  clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
  clk: qcom: Add GDSC support for SDX55 GCC
  dt-bindings: clock: Add GDSC in SDX55 GCC
  clk: qcom: Add support for SDX55 RPMh clocks
  dt-bindings: clock: Introduce RPMHCC bindings for SDX55
  clk: qcom: Add SDX55 GCC support
  dt-bindings: clock: Add SDX55 GCC clock bindings
  clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"
  clk: qcom: rpmh: Add CE clock on sdm845.
  dt-bindings: clock: Add entry for crypto engine RPMH clock resource
  clk: qcom: dispcc-sm8250: handle MMCX power domain
  clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
  clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
  clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks
  clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
  dt-bindings: clock: Add support for LPASS Always ON Controller
  ...

* clk-simplify:
  clk: remove unneeded dead-store initialization

* clk-hw:
  clk: meson: g12: use devm variant to register notifiers
  clk: add devm variant of clk_notifier_register
  clk: meson: g12: drop use of __clk_lookup()
  clk: add api to get clk consumer from clk_hw
  clk: avoid devm_clk_release name clash

* clk-renesas:
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema
  clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
  clk: renesas: r8a774c0: Add RPC clocks
  clk: renesas: r8a779a0: Fix R and OSC clocks
  clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
  clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
  clk: renesas: r8a774b1: Add RPC clocks
  clk: renesas: r8a774a1: Add RPC clocks
  clk: renesas: r8a779a0: Add VIN clocks
  clk: renesas: r8a779a0: Add CSI4[0-3] clocks
  MAINTAINERS: Update git repo for Renesas clock drivers
  clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
  clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI

* clk-samsung:
  clk: samsung: Prevent potential endless loop in the PLL ops
  clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
parents 9d1c94a6 f7b36cc1 6a178497 e6fb7aee fdc9b019 87b6a5e2

Documentation/devicetree/bindings/clock/qcom,aoncc-sm8250.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs



maintainers:

  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>



description: |

  The clock consumer should specify the desired clock by having the clock

  ID in its "clocks" phandle cell.

  See include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h for the full list

  of Audio Clock controller clock IDs.



properties:

  compatible:

    const: qcom,sm8250-lpass-aon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    items:

      - description: LPASS Core voting clock

      - description: Glitch Free Mux register clock



  clock-names:

    items:

      - const: core

      - const: bus



required:

  - compatible

  - reg

  - '#clock-cells'

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>

    #include <dt-bindings/sound/qcom,q6afe.h>

    clock-controller@3800000 {

      #clock-cells = <1>;

      compatible = "qcom,sm8250-lpass-aon";

      reg = <0x03380000 0x40000>;

      clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

               <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

      clock-names = "core", "bus";

    };

Documentation/devicetree/bindings/clock/qcom,audiocc-sm8250.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Clock bindings for LPASS Audio Clock Controller on SM8250 SoCs



maintainers:

  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>



description: |

  The clock consumer should specify the desired clock by having the clock

  ID in its "clocks" phandle cell.

  See include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h for the full list

  of Audio Clock controller clock IDs.



properties:

  compatible:

    const: qcom,sm8250-lpass-audiocc



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    items:

      - description: LPASS Core voting clock

      - description: Glitch Free Mux register clock



  clock-names:

    items:

      - const: core

      - const: bus



required:

  - compatible

  - reg

  - '#clock-cells'

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>

    #include <dt-bindings/sound/qcom,q6afe.h>

    clock-controller@3300000 {

      #clock-cells = <1>;

      compatible = "qcom,sm8250-lpass-audiocc";

      reg = <0x03300000 0x30000>;

      clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,

               <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;

      clock-names = "core", "bus";

    };

Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller Binding for SDX55



maintainers:

  - Vinod Koul <vkoul@kernel.org>

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description: |

  Qualcomm global clock control module which supports the clocks, resets and

  power domains on SDX55



  See also:

  - dt-bindings/clock/qcom,gcc-sdx55.h



properties:

  compatible:

    const: qcom,gcc-sdx55



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PLL test clock source (Optional clock)

    minItems: 2

    maxItems: 3



  clock-names:

    items:

      - const: bi_tcxo

      - const: sleep_clk

      - const: core_bi_pll_test_se # Optional clock

    minItems: 2

    maxItems: 3



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - clocks

  - clock-names

  - reg

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,gcc-sdx55";

      reg = <0x00100000 0x1f0000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&sleep_clk>, <&pll_test_clk>;

      clock-names = "bi_tcxo", "sleep_clk", "core_bi_pll_test_se";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -19,8 +19,10 @@ properties: 
    enum:

      - qcom,sc7180-rpmh-clk

      - qcom,sdm845-rpmh-clk

      - qcom,sdx55-rpmh-clk

      - qcom,sm8150-rpmh-clk

      - qcom,sm8250-rpmh-clk

      - qcom,sm8350-rpmh-clk



  clocks:

    maxItems: 1

Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Camera Clock & Reset Controller Binding for SC7180



maintainers:

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm camera clock control module which supports the clocks, resets and

  power domains on SC7180.



  See also:

  - dt-bindings/clock/qcom,camcc-sc7180.h



properties:

  compatible:

    const: qcom,sc7180-camcc



  clocks:

    items:

      - description: Board XO source

      - description: Camera_ahb clock from GCC

      - description: Camera XO clock from GCC



  clock-names:

    items:

      - const: bi_tcxo

      - const: iface

      - const: xo



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sc7180.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@ad00000 {

      compatible = "qcom,sc7180-camcc";

      reg = <0x0ad00000 0x10000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&gcc GCC_CAMERA_AHB_CLK>,

               <&gcc GCC_CAMERA_XO_CLK>;

      clock-names = "bi_tcxo", "iface", "xo";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

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