clk: qcom: rpmh: add support for SM8350 rpmh clocks (f7b36cc1) · Commits · 戴 / test

drivers/clk/qcom/clk-rpmh.c

+46 −12

Original line number	Diff line number	Diff line
		@@ -373,6 +373,25 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
		.num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
		};

		DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
		DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
		DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");

		static struct clk_hw *sdx55_rpmh_clocks[] = {
		[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
		[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
		[RPMH_RF_CLK1] = &sdx55_rf_clk1.hw,
		[RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw,
		[RPMH_RF_CLK2] = &sdx55_rf_clk2.hw,
		[RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw,
		[RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
		};

		static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
		.clks = sdx55_rpmh_clocks,
		.num_clks = ARRAY_SIZE(sdx55_rpmh_clocks),
		};

		static struct clk_hw *sm8150_rpmh_clocks[] = {
		[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
		[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
		@@ -434,23 +453,37 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
		.num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
		};

		DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1);
		DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1);
		DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0");
		DEFINE_CLK_RPMH_VRM(sm8350, div_clk1, div_clk1_ao, "divclka1", 2);
		DEFINE_CLK_RPMH_VRM(sm8350, rf_clk4, rf_clk4_ao, "rfclka4", 1);
		DEFINE_CLK_RPMH_VRM(sm8350, rf_clk5, rf_clk5_ao, "rfclka5", 1);
		DEFINE_CLK_RPMH_BCM(sm8350, pka, "PKA0");
		DEFINE_CLK_RPMH_BCM(sm8350, hwkm, "HK0");

		static struct clk_hw *sdx55_rpmh_clocks[] = {
		static struct clk_hw *sm8350_rpmh_clocks[] = {
		[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
		[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
		[RPMH_RF_CLK1] = &sdx55_rf_clk1.hw,
		[RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw,
		[RPMH_RF_CLK2] = &sdx55_rf_clk2.hw,
		[RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw,
		[RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw,
		[RPMH_DIV_CLK1] = &sm8350_div_clk1.hw,
		[RPMH_DIV_CLK1_A] = &sm8350_div_clk1_ao.hw,
		[RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
		[RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
		[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
		[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
		[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
		[RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
		[RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
		[RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
		[RPMH_RF_CLK4] = &sm8350_rf_clk4.hw,
		[RPMH_RF_CLK4_A] = &sm8350_rf_clk4_ao.hw,
		[RPMH_RF_CLK5] = &sm8350_rf_clk5.hw,
		[RPMH_RF_CLK5_A] = &sm8350_rf_clk5_ao.hw,
		[RPMH_IPA_CLK] = &sdm845_ipa.hw,
		[RPMH_PKA_CLK] = &sm8350_pka.hw,
		[RPMH_HWKM_CLK] = &sm8350_hwkm.hw,
		};

		static const struct clk_rpmh_desc clk_rpmh_sdx55 = {
		.clks = sdx55_rpmh_clocks,
		.num_clks = ARRAY_SIZE(sdx55_rpmh_clocks),
		static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
		.clks = sm8350_rpmh_clocks,
		.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
		};

		static struct clk_hw of_clk_rpmh_hw_get(struct of_phandle_args clkspec,
		@@ -541,6 +574,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
		{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
		{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
		{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
		{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
		{ }
		};
		MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);

include/dt-bindings/clock/qcom,rpmh.h

+8 −0

Original line number	Diff line number	Diff line
		@@ -23,5 +23,13 @@
		#define RPMH_LN_BB_CLK1_A 14
		#define RPMH_CE_CLK 15
		#define RPMH_QPIC_CLK 16
		#define RPMH_DIV_CLK1 17
		#define RPMH_DIV_CLK1_A 18
		#define RPMH_RF_CLK4 19
		#define RPMH_RF_CLK4_A 20
		#define RPMH_RF_CLK5 21
		#define RPMH_RF_CLK5_A 22
		#define RPMH_PKA_CLK 23
		#define RPMH_HWKM_CLK 24

		#endif

Admin message