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Commit d477c669 authored by Tomáš Juřena's avatar Tomáš Juřena Committed by Johan Hedberg
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boards: st: stm32h745i_disco: Use PLL2Q as FDCAN clock source 



With this configuration of the device tree, we use 80 MHz as
a FDCAN bus clock. This configuration allows to pass the tests.

Signed-off-by: default avatarTomáš Juřena <jurenatomas@gmail.com>
parent 9d8059b6
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