Commit e02cb1f5 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-ti', 'clk-samsung', 'clk-imx' and 'clk-allwinner' into clk-next

* clk-ti:
  clk: ti: Use int to check return value from of_property_count_elems_of_size()
  firmware: ti_sci: extend clock identifiers from u8 to u32
  clk: keystone: sci-clk: extend clock IDs to 32 bits
  clk: keystone: sci-clk: probe clocks from DT instead of firmware
  clk: keystone: sci-clk: split out the fw clock parsing to own function
  clk: keystone: sci-clk: cut down the clock name length

* clk-samsung:
  clk: samsung: Add bus clock for GPU/G3D on Exynos4412
  clk: samsung: add new clocks for DMC for Exynos5422 SoC
  clk: samsung: add BPLL rate table for Exynos 5422 SoC
  clk: samsung: add needed IDs for DMC clocks in Exynos5420
  clk: samsung: exynos5433: Use of_clk_get_parent_count()

* clk-imx: (38 commits)
  clk: imx8mq: Keep uart clocks on during system boot
  clk: imx: Remove __init for imx_register_uart_clocks() API
  clk: imx6q: fix section mismatch warning
  clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
  clk: imx8mq: Use imx_check_clocks() API directly
  clk: imx: Remove __init for imx_check_clocks() API
  clk: imx6sll: Switch to clk_hw based API
  clk: imx7d: Switch to clk_hw based API
  clk: imx6ul: Switch to clk_hw based API
  clk: imx6sx: Switch to clk_hw based API
  clk: imx6q: Switch to clk_hw based API
  clk: imx6sl: Switch to clk_hw based API
  clk: imx: Switch wrappers to clk_hw based API
  clk: imx: clk-fixup-mux: Switch to clk_hw based API
  clk: imx: clk-fixup-div: Switch to clk_hw based API
  clk: imx: clk-gate-exclusive: Switch to clk_hw based API
  clk: imx: clk-pfd: Switch to clk_hw based API
  clk: imx: clk-pllv3: Switch to clk_hw based API
  clk: imx: clk-gate2: Switch to clk_hw based API
  clk: imx: clk-cpu: Switch to clk_hw based API
  ...

* clk-allwinner: (29 commits)
  clk: Simplify debugfs printing and add a newline
  clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
  clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
  clk: sunxi-ng: gate: Add macros for referencing local clock parents
  clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
  clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
  clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
  ...
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner Clock Control Unit Device Tree Bindings

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <maxime.ripard@bootlin.com>

properties:
  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  compatible:
    enum:
      - allwinner,sun4i-a10-ccu
      - allwinner,sun5i-a10s-ccu
      - allwinner,sun5i-a13-ccu
      - allwinner,sun6i-a31-ccu
      - allwinner,sun7i-a20-ccu
      - allwinner,sun8i-a23-ccu
      - allwinner,sun8i-a33-ccu
      - allwinner,sun8i-a83t-ccu
      - allwinner,sun8i-a83t-r-ccu
      - allwinner,sun8i-h3-ccu
      - allwinner,sun8i-h3-r-ccu
      - allwinner,sun8i-r40-ccu
      - allwinner,sun8i-v3s-ccu
      - allwinner,sun9i-a80-ccu
      - allwinner,sun50i-a64-ccu
      - allwinner,sun50i-a64-r-ccu
      - allwinner,sun50i-h5-ccu
      - allwinner,sun50i-h6-ccu
      - allwinner,sun50i-h6-r-ccu
      - allwinner,suniv-f1c100s-ccu
      - nextthing,gr8-ccu

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 4
    items:
      - description: High Frequency Oscillator (usually at 24MHz)
      - description: Low Frequency Oscillator (usually at 32kHz)
      - description: Internal Oscillator
      - description: Peripherals PLL

  clock-names:
    minItems: 2
    maxItems: 4
    items:
      - const: hosc
      - const: losc
      - const: iosc
      - const: pll-periph

required:
  - "#clock-cells"
  - "#reset-cells"
  - compatible
  - reg
  - clocks
  - clock-names

if:
  properties:
    compatible:
      enum:
        - allwinner,sun8i-a83t-r-ccu
        - allwinner,sun8i-h3-r-ccu
        - allwinner,sun50i-a64-r-ccu
        - allwinner,sun50i-h6-r-ccu

then:
  properties:
    clocks:
      minItems: 4
      maxItems: 4

    clock-names:
      minItems: 4
      maxItems: 4

else:
  if:
    properties:
      compatible:
        const: allwinner,sun50i-h6-ccu

  then:
    properties:
      clocks:
        minItems: 3
        maxItems: 3

      clock-names:
        minItems: 3
        maxItems: 3

  else:
    properties:
      clocks:
        minItems: 2
        maxItems: 2

      clock-names:
        minItems: 2
        maxItems: 2

additionalProperties: false

examples:
  - |
    ccu: clock@1c20000 {
        compatible = "allwinner,sun8i-h3-ccu";
        reg = <0x01c20000 0x400>;
        clocks = <&osc24M>, <&osc32k>;
        clock-names = "hosc", "losc";
        #clock-cells = <1>;
        #reset-cells = <1>;
    };

  - |
    r_ccu: clock@1f01400 {
        compatible = "allwinner,sun50i-a64-r-ccu";
        reg = <0x01f01400 0x100>;
        clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu 11>;
        clock-names = "hosc", "losc", "iosc", "pll-periph";
        #clock-cells = <1>;
        #reset-cells = <1>;
    };

...
+0 −62
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Allwinner Clock Control Unit Binding
------------------------------------

Required properties :
- compatible: must contain one of the following compatibles:
		- "allwinner,sun4i-a10-ccu"
		- "allwinner,sun5i-a10s-ccu"
		- "allwinner,sun5i-a13-ccu"
		- "allwinner,sun6i-a31-ccu"
		- "allwinner,sun7i-a20-ccu"
		- "allwinner,sun8i-a23-ccu"
		- "allwinner,sun8i-a33-ccu"
		- "allwinner,sun8i-a83t-ccu"
		- "allwinner,sun8i-a83t-r-ccu"
		- "allwinner,sun8i-h3-ccu"
		- "allwinner,sun8i-h3-r-ccu"
+		- "allwinner,sun8i-r40-ccu"
		- "allwinner,sun8i-v3s-ccu"
		- "allwinner,sun9i-a80-ccu"
		- "allwinner,sun50i-a64-ccu"
		- "allwinner,sun50i-a64-r-ccu"
		- "allwinner,sun50i-h5-ccu"
		- "allwinner,sun50i-h6-ccu"
		- "allwinner,sun50i-h6-r-ccu"
		- "allwinner,suniv-f1c100s-ccu"
		- "nextthing,gr8-ccu"

- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
  - "hosc": the high frequency oscillator (usually at 24MHz)
  - "losc": the low frequency oscillator (usually at 32kHz)
	    On the A83T, this is the internal 16MHz oscillator divided by 512
- clock-names: Must contain the clock names described just above
- #clock-cells : must contain 1
- #reset-cells : must contain 1

For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator

For the PRCM CCUs on A83T/H3/A64/H6, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator

Example for generic CCU:
ccu: clock@1c20000 {
	compatible = "allwinner,sun8i-h3-ccu";
	reg = <0x01c20000 0x400>;
	clocks = <&osc24M>, <&osc32k>;
	clock-names = "hosc", "losc";
	#clock-cells = <1>;
	#reset-cells = <1>;
};

Example for PRCM CCU:
r_ccu: clock@1f01400 {
	compatible = "allwinner,sun50i-a64-r-ccu";
	reg = <0x01f01400 0x100>;
	clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;
	clock-names = "hosc", "losc", "iosc", "pll-periph";
	#clock-cells = <1>;
	#reset-cells = <1>;
};
+36 −2
Original line number Diff line number Diff line
@@ -2997,15 +2997,49 @@ static int clk_flags_show(struct seq_file *s, void *data)
}
DEFINE_SHOW_ATTRIBUTE(clk_flags);

static void possible_parent_show(struct seq_file *s, struct clk_core *core,
				 unsigned int i, char terminator)
{
	struct clk_core *parent;

	/*
	 * Go through the following options to fetch a parent's name.
	 *
	 * 1. Fetch the registered parent clock and use its name
	 * 2. Use the global (fallback) name if specified
	 * 3. Use the local fw_name if provided
	 * 4. Fetch parent clock's clock-output-name if DT index was set
	 *
	 * This may still fail in some cases, such as when the parent is
	 * specified directly via a struct clk_hw pointer, but it isn't
	 * registered (yet).
	 */
	parent = clk_core_get_parent_by_index(core, i);
	if (parent)
		seq_printf(s, "%s", parent->name);
	else if (core->parents[i].name)
		seq_printf(s, "%s", core->parents[i].name);
	else if (core->parents[i].fw_name)
		seq_printf(s, "<%s>(fw)", core->parents[i].fw_name);
	else if (core->parents[i].index >= 0)
		seq_printf(s, "%s",
			   of_clk_get_parent_name(core->of_node,
						  core->parents[i].index));
	else
		seq_puts(s, "(missing)");

	seq_putc(s, terminator);
}

static int possible_parents_show(struct seq_file *s, void *data)
{
	struct clk_core *core = s->private;
	int i;

	for (i = 0; i < core->num_parents - 1; i++)
		seq_printf(s, "%s ", core->parents[i].name);
		possible_parent_show(s, core, i, ' ');

	seq_printf(s, "%s\n", core->parents[i].name);
	possible_parent_show(s, core, i, '\n');

	return 0;
}
+20 −10
Original line number Diff line number Diff line
@@ -78,13 +78,14 @@ static const struct clk_ops clk_busy_divider_ops = {
	.set_rate = clk_busy_divider_set_rate,
};

struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
				 void __iomem *reg, u8 shift, u8 width,
				 void __iomem *busy_reg, u8 busy_shift)
{
	struct clk_busy_divider *busy;
	struct clk *clk;
	struct clk_hw *hw;
	struct clk_init_data init;
	int ret;

	busy = kzalloc(sizeof(*busy), GFP_KERNEL);
	if (!busy)
@@ -107,11 +108,15 @@ struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,

	busy->div.hw.init = &init;

	clk = clk_register(NULL, &busy->div.hw);
	if (IS_ERR(clk))
	hw = &busy->div.hw;

	ret = clk_hw_register(NULL, hw);
	if (ret) {
		kfree(busy);
		return ERR_PTR(ret);
	}

	return clk;
	return hw;
}

struct clk_busy_mux {
@@ -152,13 +157,14 @@ static const struct clk_ops clk_busy_mux_ops = {
	.set_parent = clk_busy_mux_set_parent,
};

struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
			     u8 width, void __iomem *busy_reg, u8 busy_shift,
			     const char * const *parent_names, int num_parents)
{
	struct clk_busy_mux *busy;
	struct clk *clk;
	struct clk_hw *hw;
	struct clk_init_data init;
	int ret;

	busy = kzalloc(sizeof(*busy), GFP_KERNEL);
	if (!busy)
@@ -181,9 +187,13 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,

	busy->mux.hw.init = &init;

	clk = clk_register(NULL, &busy->mux.hw);
	if (IS_ERR(clk))
	hw = &busy->mux.hw;

	ret = clk_hw_register(NULL, hw);
	if (ret) {
		kfree(busy);
		return ERR_PTR(ret);
	}

	return clk;
	return hw;
}
+9 −5
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@@ -75,13 +75,14 @@ static const struct clk_ops clk_cpu_ops = {
	.set_rate	= clk_cpu_set_rate,
};

struct clk *imx_clk_cpu(const char *name, const char *parent_name,
struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
		struct clk *div, struct clk *mux, struct clk *pll,
		struct clk *step)
{
	struct clk_cpu *cpu;
	struct clk *clk;
	struct clk_hw *hw;
	struct clk_init_data init;
	int ret;

	cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
	if (!cpu)
@@ -99,10 +100,13 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name,
	init.num_parents = 1;

	cpu->hw.init = &init;
	hw = &cpu->hw;

	clk = clk_register(NULL, &cpu->hw);
	if (IS_ERR(clk))
	ret = clk_hw_register(NULL, hw);
	if (ret) {
		kfree(cpu);
		return ERR_PTR(ret);
	}

	return clk;
	return hw;
}
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