Commit c0bc660c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-v5.3-samsung' of... 

Merge tag 'clk-v5.3-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung

Pull Samsung clk driver updates from Sylwester Nawrocki:

 - Addition of clocks required for new Exynos5422 Dynamic Memory
   Controller driver
 - clock definition for Exynos4412 Mali
 - minor clean up of clk-exynos5433.c

* tag 'clk-v5.3-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Add bus clock for GPU/G3D on Exynos4412
  clk: samsung: add new clocks for DMC for Exynos5422 SoC
  clk: samsung: add BPLL rate table for Exynos 5422 SoC
  clk: samsung: add needed IDs for DMC clocks in Exynos5420
  clk: samsung: exynos5433: Use of_clk_get_parent_count()
parents a188339c 7ef91224

drivers/clk/samsung/clk-exynos4.c

+1 −0
Original line number Diff line number Diff line
@@ -961,6 +961,7 @@ static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { 


/* list of gate clocks supported in exynos4x12 soc */

static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {

	GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0),

	GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),

	GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),

	GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),

drivers/clk/samsung/clk-exynos5420.c

+71 −7
Original line number Diff line number Diff line
@@ -134,6 +134,8 @@ 
#define SRC_CDREX		0x20200

#define DIV_CDREX0		0x20500

#define DIV_CDREX1		0x20504

#define GATE_BUS_CDREX0		0x20700

#define GATE_BUS_CDREX1		0x20704

#define KPLL_LOCK		0x28000

#define KPLL_CON0		0x28100

#define SRC_KFC			0x28200
@@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { 
	DIV_CDREX1,

	SRC_KFC,

	DIV_KFC0,

	GATE_BUS_CDREX0,

	GATE_BUS_CDREX1,

};



static const unsigned long exynos5800_clk_regs[] __initconst = {
@@ -425,6 +429,9 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 
PNAME(mout_group14_5800_p)	= { "dout_aclk550_cam", "dout_sclk_sw" };

PNAME(mout_group15_5800_p)	= { "dout_osc_div", "mout_sw_aclk550_cam" };

PNAME(mout_group16_5800_p)	= { "dout_osc_div", "mout_mau_epll_clk" };

PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",

					"mout_sclk_mpll", "ff_dout_spll2",

					"mout_sclk_spll", "mout_sclk_epll"};



/* fixed rate clocks generated outside the soc */

static struct samsung_fixed_rate_clock
@@ -450,7 +457,7 @@ static const struct samsung_fixed_factor_clock 
static const struct samsung_fixed_factor_clock

		exynos5800_fixed_factor_clks[] __initconst = {

	FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),

	FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),

	FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),

};



static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
@@ -472,11 +479,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 
	MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),

	MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),



	MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",

		mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),



	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",

			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),

			mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),

	MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,

			SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),

	MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),

	MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),

	MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),



	MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
@@ -648,7 +658,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 


	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),

	MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),

	MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),

	MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),

	MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),

	MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),

	MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
@@ -806,8 +816,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 
			"mout_aclk400_disp1", DIV_TOP2, 4, 3),



	/* CDREX Block */

	DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",

			DIV_CDREX0, 28, 3),

	/*

	 * The three clocks below are controlled using the same register and

	 * bits. They are put into one because there is a need of

	 * synchronization between the BUS and DREXs (two external memory

	 * interfaces).

	 * They are put here to show this HW assumption and for clock

	 * information summary completeness.

	 */

	DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",

			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),

	DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",

			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),

	DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",

			DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),



	DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",

			DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),

	DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
@@ -1170,6 +1193,32 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 
			GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),



	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),



	/* CDREX */

	GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",

			GATE_BUS_CDREX0, 0, 0, 0),

	GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",

			GATE_BUS_CDREX0, 1, 0, 0),

	GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",

			SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),



	GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",

			GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",

			GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",

			GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",

			GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),



	GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",

			GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",

			GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",

			GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",

			GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),

};



static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
@@ -1285,6 +1334,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini 
	PLL_35XX_RATE(24 * MHZ, 200000000,  200, 3, 3),

};



static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {

	PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),

	PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),

	PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),

	PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),

	PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),

	PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),

	PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),

};



static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {

	PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),

	PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
@@ -1427,9 +1487,13 @@ static void __init exynos5x_clk_init(struct device_node *np, 
		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;

		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;

		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;

		exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;

	}



	if (soc == EXYNOS5420)

		exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;

	else

		exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;



	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),

					reg_base);

	samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,

drivers/clk/samsung/clk-exynos5433.c

+2 −2
Original line number Diff line number Diff line
@@ -5590,8 +5590,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev) 
	data->nr_clk_save = info->nr_clk_regs;

	data->clk_suspend = info->suspend_regs;

	data->nr_clk_suspend = info->nr_suspend_regs;

	data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks",

						    "#clock-cells");

	data->nr_pclks = of_clk_get_parent_count(dev->of_node);



	if (data->nr_pclks > 0) {

		data->pclks = devm_kcalloc(dev, sizeof(struct clk *),

					   data->nr_pclks, GFP_KERNEL);

include/dt-bindings/clock/exynos4.h

+1 −0
Original line number Diff line number Diff line
@@ -187,6 +187,7 @@ 
#define CLK_MIPI_HSI		349 /* Exynos4210 only */

#define CLK_PIXELASYNCM0	351

#define CLK_PIXELASYNCM1	352

#define CLK_ASYNC_G3D		353 /* Exynos4x12 only */

#define CLK_PWM_ISP_SCLK	379 /* Exynos4x12 only */

#define CLK_SPI0_ISP_SCLK	380 /* Exynos4x12 only */

#define CLK_SPI1_ISP_SCLK	381 /* Exynos4x12 only */

include/dt-bindings/clock/exynos5420.h

+17 −1
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define CLK_MAU_EPLL		159

#define CLK_SCLK_HSIC_12M	160

#define CLK_SCLK_MPHY_IXTAL24	161

#define CLK_SCLK_BPLL		162



/* gate clocks */

#define CLK_UART0		257
@@ -195,6 +196,16 @@ 
#define CLK_ACLK432_CAM		518

#define CLK_ACLK_FL1550_CAM	519

#define CLK_ACLK550_CAM		520

#define CLK_CLKM_PHY0		521

#define CLK_CLKM_PHY1		522

#define CLK_ACLK_PPMU_DREX0_0	523

#define CLK_ACLK_PPMU_DREX0_1	524

#define CLK_ACLK_PPMU_DREX1_0	525

#define CLK_ACLK_PPMU_DREX1_1	526

#define CLK_PCLK_PPMU_DREX0_0	527

#define CLK_PCLK_PPMU_DREX0_1	528

#define CLK_PCLK_PPMU_DREX1_0	529

#define CLK_PCLK_PPMU_DREX1_1	530



/* mux clocks */

#define CLK_MOUT_HDMI		640
@@ -217,6 +228,8 @@ 
#define CLK_MOUT_EPLL		657

#define CLK_MOUT_MAU_EPLL	658

#define CLK_MOUT_USER_MAU_EPLL	659

#define CLK_MOUT_SCLK_SPLL	660

#define CLK_MOUT_MX_MSPLL_CCORE_PHY	661



/* divider clocks */

#define CLK_DOUT_PIXEL		768
@@ -248,8 +261,11 @@ 
#define CLK_DOUT_CCLK_DREX0	794

#define CLK_DOUT_CLK2X_PHY0	795

#define CLK_DOUT_PCLK_CORE_MEM	796

#define CLK_FF_DOUT_SPLL2	797

#define CLK_DOUT_PCLK_DREX0	798

#define CLK_DOUT_PCLK_DREX1	799



/* must be greater than maximal clock id */

#define CLK_NR_CLKS		797

#define CLK_NR_CLKS		800



#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */

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