Commit 7e9c62bd authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next 

 - Various static analysis fixes/finds
 - Video Engine (ECLK) support on Aspeed SoCs
 - Xilinx ZynqMP Versal platform support
 - Convert Xilinx ZynqMP driver to be struct oriented

* clk-sa:
  clk: mvebu: fix spelling mistake "gatable" -> "gateable"
  clk: ux500: add range to usleep_range
  clk: tegra: Make tegra_clk_super_mux_ops static
  clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5

* clk-aspeed:
  clk: Aspeed: Setup video engine clocking

* clk-samsung:
  clk: samsung: exynos5410: Add gate clock for ADC
  clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410
  clk: samsung: dt-bindings: Put CLK_UART3 in order

* clk-ingenic:
  clk: ingenic: jz4725b: Add UDC PHY clock
  dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock

* clk-zynq:
  clk: zynqmp: use structs for clk query responses
  clk: zynqmp: fix check for fractional clock
  clk: zynqmp: do not export zynqmp_clk_register_* functions
  clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents
  drivers: clk: Update clock driver to handle clock attribute
  drivers: clk: zynqmp: Allow zero divisor value
parents f6111b9d 7fbb639a defb149b aa2a0592 eaa9558d 5852b136

drivers/clk/clk-aspeed.c

+39 −3
Original line number Diff line number Diff line
@@ -87,10 +87,10 @@ struct aspeed_clk_gate { 
/* TODO: ask Aspeed about the actual parent data */

static const struct aspeed_gate_data aspeed_gates[] = {

	/*				 clk rst   name			parent	flags */

	[ASPEED_CLK_GATE_ECLK] =	{  0, -1, "eclk-gate",		"eclk",	0 }, /* Video Engine */

	[ASPEED_CLK_GATE_ECLK] =	{  0,  6, "eclk-gate",		"eclk",	0 }, /* Video Engine */

	[ASPEED_CLK_GATE_GCLK] =	{  1,  7, "gclk-gate",		NULL,	0 }, /* 2D engine */

	[ASPEED_CLK_GATE_MCLK] =	{  2, -1, "mclk-gate",		"mpll",	CLK_IS_CRITICAL }, /* SDRAM */

	[ASPEED_CLK_GATE_VCLK] =	{  3,  6, "vclk-gate",		NULL,	0 }, /* Video Capture */

	[ASPEED_CLK_GATE_VCLK] =	{  3, -1, "vclk-gate",		NULL,	0 }, /* Video Capture */

	[ASPEED_CLK_GATE_BCLK] =	{  4,  8, "bclk-gate",		"bclk",	CLK_IS_CRITICAL }, /* PCIe/PCI */

	[ASPEED_CLK_GATE_DCLK] =	{  5, -1, "dclk-gate",		NULL,	CLK_IS_CRITICAL }, /* DAC */

	[ASPEED_CLK_GATE_REFCLK] =	{  6, -1, "refclk-gate",	"clkin", CLK_IS_CRITICAL },
@@ -113,6 +113,24 @@ static const struct aspeed_gate_data aspeed_gates[] = { 
	[ASPEED_CLK_GATE_LHCCLK] =	{ 28, -1, "lhclk-gate",		"lhclk", 0 }, /* LPC master/LPC+ */

};



static const char * const eclk_parent_names[] = {

	"mpll",

	"hpll",

	"dpll",

};



static const struct clk_div_table ast2500_eclk_div_table[] = {

	{ 0x0, 2 },

	{ 0x1, 2 },

	{ 0x2, 3 },

	{ 0x3, 4 },

	{ 0x4, 5 },

	{ 0x5, 6 },

	{ 0x6, 7 },

	{ 0x7, 8 },

	{ 0 }

};



static const struct clk_div_table ast2500_mac_div_table[] = {

	{ 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */

	{ 0x1, 4 },
@@ -192,18 +210,21 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) 


struct aspeed_clk_soc_data {

	const struct clk_div_table *div_table;

	const struct clk_div_table *eclk_div_table;

	const struct clk_div_table *mac_div_table;

	struct clk_hw *(*calc_pll)(const char *name, u32 val);

};



static const struct aspeed_clk_soc_data ast2500_data = {

	.div_table = ast2500_div_table,

	.eclk_div_table = ast2500_eclk_div_table,

	.mac_div_table = ast2500_mac_div_table,

	.calc_pll = aspeed_ast2500_calc_pll,

};



static const struct aspeed_clk_soc_data ast2400_data = {

	.div_table = ast2400_div_table,

	.eclk_div_table = ast2400_div_table,

	.mac_div_table = ast2400_div_table,

	.calc_pll = aspeed_ast2400_calc_pll,

};
@@ -522,6 +543,22 @@ static int aspeed_clk_probe(struct platform_device *pdev) 
		return PTR_ERR(hw);

	aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;



	hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,

				 ARRAY_SIZE(eclk_parent_names), 0,

				 scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,

				 &aspeed_clk_lock);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;



	hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,

					   scu_base + ASPEED_CLK_SELECTION, 28,

					   3, 0, soc_data->eclk_div_table,

					   &aspeed_clk_lock);

	if (IS_ERR(hw))

		return PTR_ERR(hw);

	aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;



	/*

	 * TODO: There are a number of clocks that not included in this driver

	 * as more information is required:
@@ -531,7 +568,6 @@ static int aspeed_clk_probe(struct platform_device *pdev) 
	 *   RGMII

	 *   RMII

	 *   UART[1..5] clock source mux

	 *   Video Engine (ECLK) mux and clock divider

	 */



	for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {

drivers/clk/davinci/da8xx-cfgchip.c

+1 −3
Original line number Diff line number Diff line
@@ -160,10 +160,8 @@ static int __init da8xx_cfgchip_register_div4p5(struct device *dev, 
	struct da8xx_cfgchip_gate_clk *gate;



	gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);

	if (IS_ERR(gate))

		return PTR_ERR(gate);



	return 0;

	return PTR_ERR_OR_ZERO(gate);

}



static int __init

drivers/clk/ingenic/jz4725b-cgu.c

+6 −0
Original line number Diff line number Diff line
@@ -205,6 +205,12 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { 
		.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },

		.mux = { CGU_REG_OPCR, 2, 1},

	},



	[JZ4725B_CLK_UDC_PHY] = {

		"udc_phy", CGU_CLK_GATE,

		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },

		.gate = { CGU_REG_OPCR, 6, true },

	},

};



static void __init jz4725b_cgu_init(struct device_node *np)

drivers/clk/mvebu/common.c

+1 −1
Original line number Diff line number Diff line
@@ -240,7 +240,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np, 
	int n;



	if (ctrl) {

		pr_err("mvebu-clk-gating: cannot instantiate more than one gatable clock device\n");

		pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n");

		return;

	}

drivers/clk/mvebu/cp110-system-controller.c

+2 −2
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
 *    - Equal to SDIO clock

 *    - 2/5 PLL0

 *

 * CP110 has 32 gatable clocks, for the various peripherals in the IP.

 * CP110 has 32 gateable clocks, for the various peripherals in the IP.

 */



#define pr_fmt(fmt) "cp110-system-controller: " fmt
@@ -57,7 +57,7 @@ enum { 
#define CP110_CORE_NAND			4

#define CP110_CORE_SDIO			5



/* A number of gatable clocks need special handling */

/* A number of gateable clocks need special handling */

#define CP110_GATE_AUDIO		0

#define CP110_GATE_COMM_UNIT		1

#define CP110_GATE_NAND			2

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