Commit f6111b9d authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next 

 - Remove clk_readl() and introduce BE versions of basic clk types

* clk-doc:
  clk: Drop duplicate clk_register() documentation
  clk: Document and simplify clk_core_get_rate_nolock()
  clk: Remove 'flags' member of struct clk_fixed_rate
  clk: nxp: Drop 'flags' on fixed_rate clk macro
  clk: Document __clk_mux_determine_rate()
  clk: Document CLK_MUX_READ_ONLY mux flag
  clk: Document deprecated things
  clk: Collapse gpio clk kerneldoc

* clk-more-critical:
  clk: highbank: Convert to CLK_IS_CRITICAL

* clk-meson: (21 commits)
  clk: meson: axg-audio: add g12a support
  clk: meson: axg-audio: don't register inputs in the onecell data
  clk: meson: axg_audio: replace prefix axg by aud
  dt-bindings: clk: axg-audio: add g12a support
  clk: meson: meson8b: add the video decoder clock trees
  clk: meson: meson8b: add the VPU clock trees
  clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
  clk: meson: meson8b: use a separate clock table for Meson8m2
  dt-bindings: clock: meson8b: export the video decoder clocks
  clk: meson-g12a: add video decoder clocks
  dt-bindings: clock: meson8b: export the VPU clock
  clk: meson-g12a: add PCIE PLL clocks
  dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
  clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
  dt-bindings: clock: meson8b: drop the "ABP" clock definition
  clk: meson: g12a: add cpu clocks
  dt-bindings: clk: g12a-clkc: add VDEC clock IDs
  dt-bindings: clock: axg-audio: unexpose controller inputs
  dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
  clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
  ...

* clk-basic-be:
  clk: core: replace clk_{readl,writel} with {readl,writel}
  clk: core: remove powerpc special handling
  powerpc/512x: mark clocks as big endian
  clk: mux: add explicit big endian support
  clk: multiplier: add explicit big endian support
  clk: gate: add explicit big endian support
  clk: fractional-divider: add explicit big endian support
  clk: divider: add explicit big endian support
parents 2ed3b910 f14382d7 043f44ab 6e4fcc34 5834fd75

Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt

+2 −1
Original line number Diff line number Diff line
@@ -6,7 +6,8 @@ devices. 


Required Properties:



- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D

- compatible	: should be "amlogic,axg-audio-clkc" for the A113X and A113D,

		  "amlogic,g12a-audio-clkc" for G12A.

- reg		: physical base address of the clock controller and length of

		  memory mapped region.

- clocks	: a list of phandle + clock-specifier pairs for the clocks listed

arch/powerpc/platforms/512x/clock-commonclk.c

+6 −3
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ static inline struct clk *mpc512x_clk_divider( 
	const char *name, const char *parent_name, u8 clkflags,

	u32 __iomem *reg, u8 pos, u8 len, int divflags)

{

	divflags |= CLK_DIVIDER_BIG_ENDIAN;

	return clk_register_divider(NULL, name, parent_name, clkflags,

				    reg, pos, len, divflags, &clklock);

}
@@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable( 
{

	u8 divflags;



	divflags = 0;

	divflags = CLK_DIVIDER_BIG_ENDIAN;

	return clk_register_divider_table(NULL, name, parent_name, 0,

					  reg, pos, len, divflags,

					  divtab, &clklock);
@@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated( 
	u32 __iomem *reg, u8 pos)

{

	int clkflags;

	u8 gateflags;



	clkflags = CLK_SET_RATE_PARENT;

	gateflags = CLK_GATE_BIG_ENDIAN;

	return clk_register_gate(NULL, name, parent_name, clkflags,

				 reg, pos, 0, &clklock);

				 reg, pos, gateflags, &clklock);

}



static inline struct clk *mpc512x_clk_muxed(const char *name,
@@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name, 
	u8 muxflags;



	clkflags = CLK_SET_RATE_PARENT;

	muxflags = 0;

	muxflags = CLK_MUX_BIG_ENDIAN;

	return clk_register_mux(NULL, name,

				parent_names, parent_count, clkflags,

				reg, pos, len, muxflags, &clklock);

drivers/clk/clk-divider.c

+20 −4
Original line number Diff line number Diff line
@@ -25,6 +25,22 @@ 
 * parent - fixed parent.  No clk_set_parent support

 */



static inline u32 clk_div_readl(struct clk_divider *divider)

{

	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)

		return ioread32be(divider->reg);



	return readl(divider->reg);

}



static inline void clk_div_writel(struct clk_divider *divider, u32 val)

{

	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)

		iowrite32be(val, divider->reg);

	else

		writel(val, divider->reg);

}



static unsigned int _get_table_maxdiv(const struct clk_div_table *table,

				      u8 width)

{
@@ -135,7 +151,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, 
	struct clk_divider *divider = to_clk_divider(hw);

	unsigned int val;



	val = clk_readl(divider->reg) >> divider->shift;

	val = clk_div_readl(divider) >> divider->shift;

	val &= clk_div_mask(divider->width);



	return divider_recalc_rate(hw, parent_rate, val, divider->table,
@@ -370,7 +386,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 
	if (divider->flags & CLK_DIVIDER_READ_ONLY) {

		u32 val;



		val = clk_readl(divider->reg) >> divider->shift;

		val = clk_div_readl(divider) >> divider->shift;

		val &= clk_div_mask(divider->width);



		return divider_ro_round_rate(hw, rate, prate, divider->table,
@@ -420,11 +436,11 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {

		val = clk_div_mask(divider->width) << (divider->shift + 16);

	} else {

		val = clk_readl(divider->reg);

		val = clk_div_readl(divider);

		val &= ~(clk_div_mask(divider->width) << divider->shift);

	}

	val |= (u32)value << divider->shift;

	clk_writel(val, divider->reg);

	clk_div_writel(divider, val);



	if (divider->lock)

		spin_unlock_irqrestore(divider->lock, flags);

drivers/clk/clk-fractional-divider.c

+19 −3
Original line number Diff line number Diff line
@@ -13,6 +13,22 @@ 
#include <linux/slab.h>

#include <linux/rational.h>



static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)

{

	if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)

		return ioread32be(fd->reg);



	return readl(fd->reg);

}



static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)

{

	if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)

		iowrite32be(val, fd->reg);

	else

		writel(val, fd->reg);

}



static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,

					unsigned long parent_rate)

{
@@ -27,7 +43,7 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, 
	else

		__acquire(fd->lock);



	val = clk_readl(fd->reg);

	val = clk_fd_readl(fd);



	if (fd->lock)

		spin_unlock_irqrestore(fd->lock, flags);
@@ -115,10 +131,10 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, 
	else

		__acquire(fd->lock);



	val = clk_readl(fd->reg);

	val = clk_fd_readl(fd);

	val &= ~(fd->mmask | fd->nmask);

	val |= (m << fd->mshift) | (n << fd->nshift);

	clk_writel(val, fd->reg);

	clk_fd_writel(fd, val);



	if (fd->lock)

		spin_unlock_irqrestore(fd->lock, flags);

drivers/clk/clk-gate.c

+19 −3
Original line number Diff line number Diff line
@@ -23,6 +23,22 @@ 
 * parent - fixed parent.  No clk_set_parent support

 */



static inline u32 clk_gate_readl(struct clk_gate *gate)

{

	if (gate->flags & CLK_GATE_BIG_ENDIAN)

		return ioread32be(gate->reg);



	return readl(gate->reg);

}



static inline void clk_gate_writel(struct clk_gate *gate, u32 val)

{

	if (gate->flags & CLK_GATE_BIG_ENDIAN)

		iowrite32be(val, gate->reg);

	else

		writel(val, gate->reg);

}



/*

 * It works on following logic:

 *
@@ -55,7 +71,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) 
		if (set)

			reg |= BIT(gate->bit_idx);

	} else {

		reg = clk_readl(gate->reg);

		reg = clk_gate_readl(gate);



		if (set)

			reg |= BIT(gate->bit_idx);
@@ -63,7 +79,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) 
			reg &= ~BIT(gate->bit_idx);

	}



	clk_writel(reg, gate->reg);

	clk_gate_writel(gate, reg);



	if (gate->lock)

		spin_unlock_irqrestore(gate->lock, flags);
@@ -88,7 +104,7 @@ int clk_gate_is_enabled(struct clk_hw *hw) 
	u32 reg;

	struct clk_gate *gate = to_clk_gate(hw);



	reg = clk_readl(gate->reg);

	reg = clk_gate_readl(gate);



	/* if a set bit disables this clk, flip it before masking */

	if (gate->flags & CLK_GATE_SET_TO_DISABLE)

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