Commit 7d716bd4 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm64-dt-for-v5.7-tag1' of... 

Merge tag 'renesas-arm64-dt-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM64 DT updates for v5.7

  - CryptoCell support for R-Car M3-W, M3-W+, M3-N, E3, and D3,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm64-dt-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: rzg2: Add reset control properties for display
  arm64: dts: renesas: rcar-gen3: Add reset control properties for display
  arm64: dts: renesas: Remove use of ARCH_R8A7795
  arm64: dts: renesas: rcar-gen3: Add CCREE nodes
  arm64: dts: renesas: rcar-gen3: Replace "vsps" by "renesas,vsps"
  arm: dts: renesas: r8a77980: Remove r8a77970 DU compatible

Link: https://lore.kernel.org/r/20200226110221.19288-5-geert+renesas@glider.be


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3cd3fabd 721b7619

arch/arm64/boot/dts/renesas/Makefile

+0 −4
Original line number Diff line number Diff line
@@ -5,10 +5,6 @@ dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb 
dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb

dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb \

			       r8a774c0-ek874-idk-2121wr.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a77950-salvator-x.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a77951-ulcb.dtb r8a77951-ulcb-kf.dtb

dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb

dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb r8a77950-ulcb-kf.dtb

dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb r8a77951-salvator-xs.dtb

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -2634,13 +2634,14 @@ 
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>,

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,

				 <&cpg CPG_MOD 722>;

			clock-names = "du.0", "du.1", "du.2";

			resets = <&cpg 724>, <&cpg 722>;

			reset-names = "du.0", "du.2";

			status = "disabled";



			vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;

			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;



			ports {

				#address-cells = <1>;

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -2480,13 +2480,14 @@ 
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>,

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,

				 <&cpg CPG_MOD 721>;

			clock-names = "du.0", "du.1", "du.3";

			resets = <&cpg 724>, <&cpg 722>;

			reset-names = "du.0", "du.3";

			status = "disabled";



			vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;

			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;



			ports {

				#address-cells = <1>;

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+5 −3
Original line number Diff line number Diff line
@@ -1810,10 +1810,12 @@ 
			reg = <0 0xfeb00000 0 0x40000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>;

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;

			clock-names = "du.0", "du.1";

			vsps = <&vspd0 0>, <&vspd1 0>;

			resets = <&cpg 724>;

			reset-names = "du.0";

			renesas,vsps = <&vspd0 0>, <&vspd1 0>;



			status = "disabled";



			ports {

arch/arm64/boot/dts/renesas/r8a77950.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
};



&du {

	vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;

	renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>;

};



&fcpvb1 {

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