Commit 3cd3fabd authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm-dt-for-v5.7-tag1' of... 

Merge tag 'renesas-arm-dt-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.7

  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  ARM: dts: rzg1: Add reset control properties for display
  ARM: dts: rcar-gen2: Add reset control properties for display
  ARM: dts: r8a7745: Convert to new DU DT bindings
  ARM: dts: r7s72100: Add SPIBSC clocks
  ARM: dts: renesas: Group tuples in operating-points properties
  ARM: dts: renesas: Add missing ethernet PHY reset GPIO on Gen2 reference boards

Link: https://lore.kernel.org/r/20200226110221.19288-2-geert+renesas@glider.be


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 98d54f81 9e123263

arch/arm/boot/dts/r7s72100-gr-peach.dts

+3 −0
Original line number Diff line number Diff line
@@ -41,6 +41,9 @@ 
		bank-width = <4>;

		device-width = <1>;



		clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;

		power-domains = <&cpg_clocks>;



		#address-cells = <1>;

		#size-cells = <1>;

arch/arm/boot/dts/r7s72100.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -467,11 +467,12 @@ 
			#clock-cells = <1>;

			compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";

			reg = <0xfcfe0438 4>;

			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;

			clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;

			clock-indices = <

				R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3

				R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1

			>;

			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";

			clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";

		};



		mstp10_clks: mstp10_clks@fcfe043c {

arch/arm/boot/dts/r8a73a4-ape6evm.dts

+2 −5
Original line number Diff line number Diff line
@@ -157,11 +157,8 @@ 


&cpu0 {

	cpu0-supply = <&vdd_dvfs>;

	operating-points = <

		/* kHz  uV */

		1950000 1115000

		1462500  995000

	>;

	operating-points = <1950000 1115000>,	/* kHz  uV */

			   <1462500  995000>;

	voltage-tolerance = <1>; /* 1% */

};

arch/arm/boot/dts/r8a7743.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -1669,9 +1669,10 @@ 
			reg = <0 0xfeb00000 0 0x40000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>;

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;

			clock-names = "du.0", "du.1";

			resets = <&cpg 724>;

			reset-names = "du.0";

			status = "disabled";



			ports {

arch/arm/boot/dts/r8a7744.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -1655,9 +1655,10 @@ 
			reg = <0 0xfeb00000 0 0x40000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>;

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;

			clock-names = "du.0", "du.1";

			resets = <&cpg 724>;

			reset-names = "du.0";

			status = "disabled";



			ports {

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