Commit 721b7619 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

arm64: dts: renesas: rzg2: Add reset control properties for display 



Add reset control properties to the device nodes for the Display Units
on all supported RZ/G2 SoCs.  Note that on these SoCs, there is only a
single reset for each pair of DU channels.

Join the clocks lines while at it, to increase uniformity.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200218133019.22299-5-geert+renesas@glider.be
parent d745c72d

arch/arm64/boot/dts/renesas/r8a774a1.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -2634,10 +2634,11 @@ 
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>,

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,

				 <&cpg CPG_MOD 722>;

			clock-names = "du.0", "du.1", "du.2";

			resets = <&cpg 724>, <&cpg 722>;

			reset-names = "du.0", "du.2";

			status = "disabled";



			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;

arch/arm64/boot/dts/renesas/r8a774b1.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -2480,10 +2480,11 @@ 
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>,

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,

				 <&cpg CPG_MOD 721>;

			clock-names = "du.0", "du.1", "du.3";

			resets = <&cpg 724>, <&cpg 722>;

			reset-names = "du.0", "du.3";

			status = "disabled";



			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -1810,9 +1810,10 @@ 
			reg = <0 0xfeb00000 0 0x40000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>,

				 <&cpg CPG_MOD 723>;

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;

			clock-names = "du.0", "du.1";

			resets = <&cpg 724>;

			reset-names = "du.0";

			renesas,vsps = <&vspd0 0>, <&vspd1 0>;



			status = "disabled";

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