Commit 6be22809 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branches 'for-next/elf-hwcap-docs', 'for-next/smccc-conduit-cleanup',... 

Merge branches 'for-next/elf-hwcap-docs', 'for-next/smccc-conduit-cleanup', 'for-next/zone-dma', 'for-next/relax-icc_pmr_el1-sync', 'for-next/double-page-fault', 'for-next/misc', 'for-next/kselftest-arm64-signal' and 'for-next/kaslr-diagnostics' into for-next/core

* for-next/elf-hwcap-docs:
  : Update the arm64 ELF HWCAP documentation
  docs/arm64: cpu-feature-registers: Rewrite bitfields that don't follow [e, s]
  docs/arm64: cpu-feature-registers: Documents missing visible fields
  docs/arm64: elf_hwcaps: Document HWCAP_SB
  docs/arm64: elf_hwcaps: sort the HWCAP{, 2} documentation by ascending value

* for-next/smccc-conduit-cleanup:
  : SMC calling convention conduit clean-up
  firmware: arm_sdei: use common SMCCC_CONDUIT_*
  firmware/psci: use common SMCCC_CONDUIT_*
  arm: spectre-v2: use arm_smccc_1_1_get_conduit()
  arm64: errata: use arm_smccc_1_1_get_conduit()
  arm/arm64: smccc/psci: add arm_smccc_1_1_get_conduit()

* for-next/zone-dma:
  : Reintroduction of ZONE_DMA for Raspberry Pi 4 support
  arm64: mm: reserve CMA and crashkernel in ZONE_DMA32
  dma/direct: turn ARCH_ZONE_DMA_BITS into a variable
  arm64: Make arm64_dma32_phys_limit static
  arm64: mm: Fix unused variable warning in zone_sizes_init
  mm: refresh ZONE_DMA and ZONE_DMA32 comments in 'enum zone_type'
  arm64: use both ZONE_DMA and ZONE_DMA32
  arm64: rename variables used to calculate ZONE_DMA32's size
  arm64: mm: use arm64_dma_phys_limit instead of calling max_zone_dma_phys()

* for-next/relax-icc_pmr_el1-sync:
  : Relax ICC_PMR_EL1 (GICv3) accesses when ICC_CTLR_EL1.PMHE is clear
  arm64: Document ICC_CTLR_EL3.PMHE setting requirements
  arm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear

* for-next/double-page-fault:
  : Avoid a double page fault in __copy_from_user_inatomic() if hw does not support auto Access Flag
  mm: fix double page fault on arm64 if PTE_AF is cleared
  x86/mm: implement arch_faults_on_old_pte() stub on x86
  arm64: mm: implement arch_faults_on_old_pte() on arm64
  arm64: cpufeature: introduce helper cpu_has_hw_af()

* for-next/misc:
  : Various fixes and clean-ups
  arm64: kpti: Add NVIDIA's Carmel core to the KPTI whitelist
  arm64: mm: Remove MAX_USER_VA_BITS definition
  arm64: mm: simplify the page end calculation in __create_pgd_mapping()
  arm64: print additional fault message when executing non-exec memory
  arm64: psci: Reduce the waiting time for cpu_psci_cpu_kill()
  arm64: pgtable: Correct typo in comment
  arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1
  arm64: cpufeature: Fix typos in comment
  arm64/mm: Poison initmem while freeing with free_reserved_area()
  arm64: use generic free_initrd_mem()
  arm64: simplify syscall wrapper ifdeffery

* for-next/kselftest-arm64-signal:
  : arm64-specific kselftest support with signal-related test-cases
  kselftest: arm64: fake_sigreturn_misaligned_sp
  kselftest: arm64: fake_sigreturn_bad_size
  kselftest: arm64: fake_sigreturn_duplicated_fpsimd
  kselftest: arm64: fake_sigreturn_missing_fpsimd
  kselftest: arm64: fake_sigreturn_bad_size_for_magic0
  kselftest: arm64: fake_sigreturn_bad_magic
  kselftest: arm64: add helper get_current_context
  kselftest: arm64: extend test_init functionalities
  kselftest: arm64: mangle_pstate_invalid_mode_el[123][ht]
  kselftest: arm64: mangle_pstate_invalid_daif_bits
  kselftest: arm64: mangle_pstate_invalid_compat_toggle and common utils
  kselftest: arm64: extend toplevel skeleton Makefile

* for-next/kaslr-diagnostics:
  : Provide diagnostics on boot for KASLR
  arm64: kaslr: Check command line before looking for a seed
  arm64: kaslr: Announce KASLR status on boot
parents 51effa6d 478016c3 e6ea4651 bff3b044 7e3a57fa 83d116c5 918e1946 3f484ce3 2203e1ad

Documentation/arm64/booting.rst

+3 −0
Original line number Diff line number Diff line
@@ -213,6 +213,9 @@ Before jumping into the kernel, the following conditions must be met: 


      - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.

      - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.

      - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across

        all CPUs the kernel is executing on, and must stay constant

        for the lifetime of the kernel.



  - If the kernel is entered at EL1:

Documentation/arm64/cpu-feature-registers.rst

+15 −4
Original line number Diff line number Diff line
@@ -168,8 +168,15 @@ infrastructure: 
     +------------------------------+---------+---------+





  3) MIDR_EL1 - Main ID Register

  3) ID_AA64PFR1_EL1 - Processor Feature Register 1

     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | SSBS                         | [7-4]   |    y    |

     +------------------------------+---------+---------+





  4) MIDR_EL1 - Main ID Register

     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+
@@ -188,11 +195,15 @@ infrastructure: 
   as available on the CPU where it is fetched and is not a system

   wide safe value.



  4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1

  5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | SB                           | [39-36] |    y    |

     +------------------------------+---------+---------+

     | FRINTTS                      | [35-32] |    y    |

     +------------------------------+---------+---------+

     | GPI                          | [31-28] |    y    |

     +------------------------------+---------+---------+

     | GPA                          | [27-24] |    y    |
@@ -210,7 +221,7 @@ infrastructure: 
     | DPB                          | [3-0]   |    y    |

     +------------------------------+---------+---------+



  5) ID_AA64MMFR2_EL1 - Memory model feature register 2

  6) ID_AA64MMFR2_EL1 - Memory model feature register 2



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |
@@ -218,7 +229,7 @@ infrastructure: 
     | AT                           | [35-32] |    y    |

     +------------------------------+---------+---------+



  6) ID_AA64ZFR0_EL1 - SVE feature ID register 0

  7) ID_AA64ZFR0_EL1 - SVE feature ID register 0



     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

Documentation/arm64/elf_hwcaps.rst

+35 −32
Original line number Diff line number Diff line
@@ -119,10 +119,6 @@ HWCAP_LRCPC 
HWCAP_DCPOP

    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0001.



HWCAP2_DCPODP



    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.



HWCAP_SHA3

    Functionality implied by ID_AA64ISAR0_EL1.SHA3 == 0b0001.
@@ -141,30 +137,6 @@ HWCAP_SHA512 
HWCAP_SVE

    Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.



HWCAP2_SVE2



    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.



HWCAP2_SVEAES



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.



HWCAP2_SVEPMULL



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.



HWCAP2_SVEBITPERM



    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.



HWCAP2_SVESHA3



    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.



HWCAP2_SVESM4



    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.



HWCAP_ASIMDFHM

   Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0001.
@@ -180,13 +152,12 @@ HWCAP_ILRCPC 
HWCAP_FLAGM

    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0001.



HWCAP2_FLAGM2



    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.



HWCAP_SSBS

    Functionality implied by ID_AA64PFR1_EL1.SSBS == 0b0010.



HWCAP_SB

    Functionality implied by ID_AA64ISAR1_EL1.SB == 0b0001.



HWCAP_PACA

    Functionality implied by ID_AA64ISAR1_EL1.APA == 0b0001 or

    ID_AA64ISAR1_EL1.API == 0b0001, as described by
@@ -197,6 +168,38 @@ HWCAP_PACG 
    ID_AA64ISAR1_EL1.GPI == 0b0001, as described by

    Documentation/arm64/pointer-authentication.rst.



HWCAP2_DCPODP



    Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.



HWCAP2_SVE2



    Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.



HWCAP2_SVEAES



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.



HWCAP2_SVEPMULL



    Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.



HWCAP2_SVEBITPERM



    Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.



HWCAP2_SVESHA3



    Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.



HWCAP2_SVESM4



    Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.



HWCAP2_FLAGM2



    Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.



HWCAP2_FRINT



    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.

arch/arm/mm/proc-v7-bugs.c

+3 −7
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

#include <linux/arm-smccc.h>

#include <linux/kernel.h>

#include <linux/psci.h>

#include <linux/smp.h>



#include <asm/cp15.h>
@@ -75,11 +74,8 @@ static void cpu_v7_spectre_init(void) 
	case ARM_CPU_PART_CORTEX_A72: {

		struct arm_smccc_res res;



		if (psci_ops.smccc_version == SMCCC_VERSION_1_0)

			break;



		switch (psci_ops.conduit) {

		case PSCI_CONDUIT_HVC:

		switch (arm_smccc_1_1_get_conduit()) {

		case SMCCC_CONDUIT_HVC:

			arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,

					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);

			if ((int)res.a0 != 0)
@@ -90,7 +86,7 @@ static void cpu_v7_spectre_init(void) 
			spectre_v2_method = "hypervisor";

			break;



		case PSCI_CONDUIT_SMC:

		case SMCCC_CONDUIT_SMC:

			arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,

					  ARM_SMCCC_ARCH_WORKAROUND_1, &res);

			if ((int)res.a0 != 0)

arch/arm64/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -268,6 +268,10 @@ config GENERIC_CSUM 
config GENERIC_CALIBRATE_DELAY

	def_bool y



config ZONE_DMA

	bool "Support DMA zone" if EXPERT

	default y



config ZONE_DMA32

	bool "Support DMA32 zone" if EXPERT

	default y

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