Commit 51effa6d authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/perf' into for-next/core 

- Support for additional PMU topologies on HiSilicon platforms
- Support for CCN-512 interconnect PMU
- Support for AXI ID filtering in the IMX8 DDR PMU
- Support for the CCPI2 uncore PMU in ThunderX2
- Driver cleanup to use devm_platform_ioremap_resource()

* for-next/perf:
  drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform
  perf/imx_ddr: Dump AXI ID filter info to userspace
  docs/perf: Add AXI ID filter capabilities information
  perf/imx_ddr: Add driver for DDR PMU in i.MX8MPlus
  perf/imx_ddr: Add enhanced AXI ID filter support
  bindings: perf: imx-ddr: Add new compatible string
  docs/perf: Add explanation for DDR_CAP_AXI_ID_FILTER_ENHANCED quirk
  arm64: perf: Simplify the ARMv8 PMUv3 event attributes
  drivers/perf: Add CCPI2 PMU support in ThunderX2 UNCORE driver.
  Documentation: perf: Update documentation for ThunderX2 PMU uncore driver
  Documentation: Add documentation for CCN-512 DTS binding
  perf: arm-ccn: Enable stats for CCN-512 interconnect
  perf/smmuv3: use devm_platform_ioremap_resource() to simplify code
  perf/arm-cci: use devm_platform_ioremap_resource() to simplify code
  perf/arm-ccn: use devm_platform_ioremap_resource() to simplify code
  perf: xgene: use devm_platform_ioremap_resource() to simplify code
  perf: hisi: use devm_platform_ioremap_resource() to simplify code
parents c1c9ea63 8703317a

Documentation/admin-guide/perf/imx-ddr.rst

+12 −3
Original line number Diff line number Diff line
@@ -17,7 +17,8 @@ The "format" directory describes format of the config (event ID) and config1 
(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/

devices/imx8_ddr0/format/. The "events" directory describes the events types

hardware supported that can be used with perf tool, see /sys/bus/event_source/

devices/imx8_ddr0/events/.

devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented

in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.

  e.g.::

        perf stat -a -e imx8_ddr0/cycles/ cmd

        perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
@@ -25,9 +26,12 @@ devices/imx8_ddr0/events/. 
AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)

to count reading or writing matches filter setting. Filter setting is various

from different DRAM controller implementations, which is distinguished by quirks

in the driver.

in the driver. You also can dump info from userspace, filter in "caps" directory

indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates

whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and

value 1 for supported.



* With DDR_CAP_AXI_ID_FILTER quirk.

* With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0).

  Filter is defined with two configuration parts:

  --AXI_ID defines AxID matching value.

  --AXI_MASKING defines which bits of AxID are meaningful for the matching.
@@ -50,3 +54,8 @@ in the driver. 
  axi_id to monitor a specific id, rather than having to specify axi_mask.

  e.g.::

        perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12



* With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1).

  This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits

  counting the number of bytes (as opposed to the number of bursts) from DDR

  read and write transactions concurrently with another set of data counters.

Documentation/admin-guide/perf/thunderx2-pmu.rst

+11 −9
Original line number Diff line number Diff line
@@ -3,24 +3,26 @@ Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) 
=============================================================



The ThunderX2 SoC PMU consists of independent, system-wide, per-socket

PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC).

PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and

Cavium Coherent Processor Interconnect (CCPI2).



The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.

Events are counted for the default channel (i.e. channel 0) and prorated

to the total number of channels/tiles.



The DMC and L3C support up to 4 counters. Counters are independently

programmable and can be started and stopped individually. Each counter

can be set to a different event. Counters are 32-bit and do not support

an overflow interrupt; they are read every 2 seconds.

The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8

counters. Counters are independently programmable to different events and

can be started and stopped individually. None of the counters support an

overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.

The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.



PMU UNCORE (perf) driver:



The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and

L3C devices.  Each PMU can be used to count up to 4 events

simultaneously. The PMUs provide a description of their available events

and configuration options under sysfs, see

/sys/devices/uncore_<l3c_S/dmc_S/>; S is the socket id.

L3C devices.  Each PMU can be used to count up to 4 (DMC/L3C) or up to 8

(CCPI2) events simultaneously. The PMUs provide a description of their

available events and configuration options under sysfs, see

/sys/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.



The driver does not support sampling, therefore "perf record" will not

work. Per-task perf sessions are also not supported.

Documentation/devicetree/bindings/perf/arm-ccn.txt

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ Required properties: 
	"arm,ccn-502"

	"arm,ccn-504"

	"arm,ccn-508"

	"arm,ccn-512"



- reg: (standard registers property) physical address and size

	(16MB) of the configuration registers block

Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt

+1 −0
Original line number Diff line number Diff line
@@ -5,6 +5,7 @@ Required properties: 
- compatible: should be one of:

	"fsl,imx8-ddr-pmu"

	"fsl,imx8m-ddr-pmu"

	"fsl,imx8mp-ddr-pmu"



- reg: physical address and size

arch/arm64/kernel/perf_event.c

+66 −125
Original line number Diff line number Diff line
@@ -159,132 +159,73 @@ armv8pmu_events_sysfs_show(struct device *dev, 
}



#define ARMV8_EVENT_ATTR(name, config)						\

	PMU_EVENT_ATTR(name, armv8_event_attr_##name, \

		       config, armv8pmu_events_sysfs_show)



ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);

ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);

ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);

ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);

ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);

ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);

ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);

ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);

ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);

ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);

ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);

ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);

ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);

ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);

ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);

ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);

ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);

ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);

ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);

ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);

ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);

ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);

ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);

ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);

ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);

ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);

ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);

ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);

ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);

ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);

/* Don't expose the chain event in /sys, since it's useless in isolation */

ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);

ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);

ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);

ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);

ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);

ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);

ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);

ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);

ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);

ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);

ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);

ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);

ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);

ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);

ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);

ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);

ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);

ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);

ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS);

ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE);

ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS);

ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK);

ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK);

ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD);

ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD);

ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD);

ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP);

ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED);

ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE);

ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION);

	(&((struct perf_pmu_events_attr) {					\

		.attr = __ATTR(name, 0444, armv8pmu_events_sysfs_show, NULL),	\

		.id = config,							\

	}).attr.attr)



static struct attribute *armv8_pmuv3_event_attrs[] = {

	&armv8_event_attr_sw_incr.attr.attr,

	&armv8_event_attr_l1i_cache_refill.attr.attr,

	&armv8_event_attr_l1i_tlb_refill.attr.attr,

	&armv8_event_attr_l1d_cache_refill.attr.attr,

	&armv8_event_attr_l1d_cache.attr.attr,

	&armv8_event_attr_l1d_tlb_refill.attr.attr,

	&armv8_event_attr_ld_retired.attr.attr,

	&armv8_event_attr_st_retired.attr.attr,

	&armv8_event_attr_inst_retired.attr.attr,

	&armv8_event_attr_exc_taken.attr.attr,

	&armv8_event_attr_exc_return.attr.attr,

	&armv8_event_attr_cid_write_retired.attr.attr,

	&armv8_event_attr_pc_write_retired.attr.attr,

	&armv8_event_attr_br_immed_retired.attr.attr,

	&armv8_event_attr_br_return_retired.attr.attr,

	&armv8_event_attr_unaligned_ldst_retired.attr.attr,

	&armv8_event_attr_br_mis_pred.attr.attr,

	&armv8_event_attr_cpu_cycles.attr.attr,

	&armv8_event_attr_br_pred.attr.attr,

	&armv8_event_attr_mem_access.attr.attr,

	&armv8_event_attr_l1i_cache.attr.attr,

	&armv8_event_attr_l1d_cache_wb.attr.attr,

	&armv8_event_attr_l2d_cache.attr.attr,

	&armv8_event_attr_l2d_cache_refill.attr.attr,

	&armv8_event_attr_l2d_cache_wb.attr.attr,

	&armv8_event_attr_bus_access.attr.attr,

	&armv8_event_attr_memory_error.attr.attr,

	&armv8_event_attr_inst_spec.attr.attr,

	&armv8_event_attr_ttbr_write_retired.attr.attr,

	&armv8_event_attr_bus_cycles.attr.attr,

	&armv8_event_attr_l1d_cache_allocate.attr.attr,

	&armv8_event_attr_l2d_cache_allocate.attr.attr,

	&armv8_event_attr_br_retired.attr.attr,

	&armv8_event_attr_br_mis_pred_retired.attr.attr,

	&armv8_event_attr_stall_frontend.attr.attr,

	&armv8_event_attr_stall_backend.attr.attr,

	&armv8_event_attr_l1d_tlb.attr.attr,

	&armv8_event_attr_l1i_tlb.attr.attr,

	&armv8_event_attr_l2i_cache.attr.attr,

	&armv8_event_attr_l2i_cache_refill.attr.attr,

	&armv8_event_attr_l3d_cache_allocate.attr.attr,

	&armv8_event_attr_l3d_cache_refill.attr.attr,

	&armv8_event_attr_l3d_cache.attr.attr,

	&armv8_event_attr_l3d_cache_wb.attr.attr,

	&armv8_event_attr_l2d_tlb_refill.attr.attr,

	&armv8_event_attr_l2i_tlb_refill.attr.attr,

	&armv8_event_attr_l2d_tlb.attr.attr,

	&armv8_event_attr_l2i_tlb.attr.attr,

	&armv8_event_attr_remote_access.attr.attr,

	&armv8_event_attr_ll_cache.attr.attr,

	&armv8_event_attr_ll_cache_miss.attr.attr,

	&armv8_event_attr_dtlb_walk.attr.attr,

	&armv8_event_attr_itlb_walk.attr.attr,

	&armv8_event_attr_ll_cache_rd.attr.attr,

	&armv8_event_attr_ll_cache_miss_rd.attr.attr,

	&armv8_event_attr_remote_access_rd.attr.attr,

	&armv8_event_attr_sample_pop.attr.attr,

	&armv8_event_attr_sample_feed.attr.attr,

	&armv8_event_attr_sample_filtrate.attr.attr,

	&armv8_event_attr_sample_collision.attr.attr,

	ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),

	ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),

	ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),

	ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),

	ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),

	ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),

	ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),

	ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),

	ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),

	ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),

	ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),

	ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),

	ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),

	ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),

	ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),

	ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),

	ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),

	ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),

	ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),

	ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),

	ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),

	ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),

	ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),

	ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),

	ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),

	ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),

	ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),

	ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),

	ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),

	ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),

	/* Don't expose the chain event in /sys, since it's useless in isolation */

	ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),

	ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),

	ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),

	ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),

	ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),

	ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),

	ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),

	ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),

	ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),

	ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),

	ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),

	ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),

	ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),

	ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),

	ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),

	ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),

	ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),

	ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),

	ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),

	ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),

	ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),

	ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),

	ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),

	ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),

	ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),

	ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),

	ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),

	ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),

	ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),

	ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),

	NULL,

};

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