drm/i915: Use engine wa list for Wa_1607090982 (3873fd1a) · Commits · 戴 / test

This is in mcr range of register, thus we can only verify it through mmio. Use engine wa list with mcr range verification skip. Fixes: ("drm/i915: Implement Wa_1607090982") Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:

Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:

Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:

Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20200212165707.11143-1-mika.kuoppala@linux.intel.com

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -598,9 +598,6 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
		wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
		IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
		FF_MODE2_TDS_TIMER_MASK);

		/* Wa_1606931601:tgl */
		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
		}

		static void
		@@ -1360,6 +1357,11 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal)
		wa_write_or(wal,
		GEN7_FF_THREAD_MODE,
		GEN12_FF_TESSELATION_DOP_GATE_DISABLE);

		/* Wa_1606931601:tgl */
		wa_masked_en(wal,
		GEN7_ROW_CHICKEN2,
		GEN12_DISABLE_EARLY_READ);
		}

		if (IS_GEN(i915, 11)) {

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