Commit 0db1a5f8 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915: Implement Wa_1607090982 



SIMD16 with Src0 scalar might conflict between Src1/Src2 and cause
GRF read issue. Workaround this issue by setting bit 14 in 0xe4f4
which will disable early read/src swap of Src0.

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200207155138.30978-2-mika.kuoppala@linux.intel.com
parent 561db829

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −0
Original line number Diff line number Diff line
@@ -598,6 +598,9 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine, 
	wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,

	       IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :

			    FF_MODE2_TDS_TIMER_MASK);



	/* Wa_1606931601:tgl */

	WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);

}



static void

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -9148,6 +9148,8 @@ enum { 
#define   DISABLE_EARLY_EOT			(1 << 1)



#define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)

#define GEN12_DISABLE_EARLY_READ	BIT(14)



#define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)

#define   DOP_CLOCK_GATING_DISABLE	(1 << 0)

#define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)

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