drm/i915/gt: Expand bad CS completion event debug (c616d238) · Commits · 戴 / test

drivers/gpu/drm/i915/gt/intel_context.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -116,7 +116,8 @@ int __intel_context_do_pin(struct intel_context *ce)
		if (unlikely(err))
		goto err_active;

		CE_TRACE(ce, "pin ring:{head:%04x, tail:%04x}\n",
		CE_TRACE(ce, "pin ring:{start:%08x, head:%04x, tail:%04x}\n",
		i915_ggtt_offset(ce->ring->vma),
		ce->ring->head, ce->ring->tail);

		smp_mb__before_atomic(); /* flush pin before it is visible */

+29 −2

Original line number	Diff line number	Diff line
		@@ -2328,8 +2328,35 @@ static void process_csb(struct intel_engine_cs *engine)
		* coherent (visible from the CPU) before the
		* user interrupt and CSB is processed.
		*/
		GEM_BUG_ON(!i915_request_completed(*execlists->active) &&
		!reset_in_progress(execlists));
		if (GEM_SHOW_DEBUG() &&
		!i915_request_completed(*execlists->active) &&
		!reset_in_progress(execlists)) {
		struct i915_request rq = execlists->active;
		const u32 *regs = rq->context->lrc_reg_state;

		ENGINE_TRACE(engine,
		"ring:{start:0x%08x, head:%04x, tail:%04x, ctl:%08x, mode:%08x}\n",
		ENGINE_READ(engine, RING_START),
		ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR,
		ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR,
		ENGINE_READ(engine, RING_CTL),
		ENGINE_READ(engine, RING_MI_MODE));
		ENGINE_TRACE(engine,
		"rq:{start:%08x, head:%04x, tail:%04x, seqno:%llx:%d, hwsp:%d}, ",
		i915_ggtt_offset(rq->ring->vma),
		rq->head, rq->tail,
		rq->fence.context,
		lower_32_bits(rq->fence.seqno),
		hwsp_seqno(rq));
		ENGINE_TRACE(engine,
		"ctx:{start:%08x, head:%04x, tail:%04x}, ",
		regs[CTX_RING_START],
		regs[CTX_RING_HEAD],
		regs[CTX_RING_TAIL]);

		GEM_BUG_ON("context completed before request");
		}

		execlists_schedule_out(*execlists->active++);

		GEM_BUG_ON(execlists->active - execlists->inflight >