Commit 36851edd authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-match-string', 'clk-ingenic', 'clk-si544-round-fix' and... 

Merge branches 'clk-match-string', 'clk-ingenic', 'clk-si544-round-fix' and 'clk-bcm-stingray' into clk-next

* clk-match-string:
  clk: use match_string() helper
  clk: bcm2835: use match_string() helper

* clk-ingenic:
  clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
  clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
  clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
  clk: ingenic: jz4770: Change OTG from custom to standard gated clock
  clk: ingenic: Support specifying "wait for clock stable" delay
  clk: ingenic: Add support for clocks whose gate bit is inverted

* clk-si544-round-fix:
  clk-si544: Properly round requested frequency to nearest match

* clk-bcm-stingray:
  clk: bcm: Update and add Stingray clock entries
  dt-bindings: clk: Update Stingray binding doc
parents ef1ae470 d6347445 6ee3d385 4d3f36c5 5afa881c

Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt

+14 −12
Original line number Diff line number Diff line
@@ -276,36 +276,38 @@ These clock IDs are defined in: 
    clk_ts_500_ref	genpll2		2	BCM_SR_GENPLL2_TS_500_REF_CLK

    clk_125_nitro	genpll2		3	BCM_SR_GENPLL2_125_NITRO_CLK

    clk_chimp		genpll2		4	BCM_SR_GENPLL2_CHIMP_CLK

    clk_nic_flash	genpll2		5	BCM_SR_GENPLL2_NIC_FLASH

    clk_nic_flash	genpll2		5	BCM_SR_GENPLL2_NIC_FLASH_CLK

    clk_fs		genpll2		6	BCM_SR_GENPLL2_FS_CLK



    genpll3		crystal		0	BCM_SR_GENPLL3

    clk_hsls		genpll3		1	BCM_SR_GENPLL3_HSLS_CLK

    clk_sdio		genpll3		2	BCM_SR_GENPLL3_SDIO_CLK



    genpll4		crystal		0	BCM_SR_GENPLL4

    ccn			genpll4		1	BCM_SR_GENPLL4_CCN_CLK

    clk_ccn		genpll4		1	BCM_SR_GENPLL4_CCN_CLK

    clk_tpiu_pll	genpll4		2	BCM_SR_GENPLL4_TPIU_PLL_CLK

    noc_clk		genpll4		3	BCM_SR_GENPLL4_NOC_CLK

    clk_noc		genpll4		3	BCM_SR_GENPLL4_NOC_CLK

    clk_chclk_fs4	genpll4		4	BCM_SR_GENPLL4_CHCLK_FS4_CLK

    clk_bridge_fscpu	genpll4		5	BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK





    genpll5		crystal		0	BCM_SR_GENPLL5

    fs4_hf_clk		genpll5		1	BCM_SR_GENPLL5_FS4_HF_CLK

    crypto_ae_clk	genpll5		2	BCM_SR_GENPLL5_CRYPTO_AE_CLK

    raid_ae_clk		genpll5		3	BCM_SR_GENPLL5_RAID_AE_CLK

    clk_fs4_hf		genpll5		1	BCM_SR_GENPLL5_FS4_HF_CLK

    clk_crypto_ae	genpll5		2	BCM_SR_GENPLL5_CRYPTO_AE_CLK

    clk_raid_ae		genpll5		3	BCM_SR_GENPLL5_RAID_AE_CLK



    genpll6		crystal		0	BCM_SR_GENPLL6

    48_usb		genpll6		1	BCM_SR_GENPLL6_48_USB_CLK

    clk_48_usb		genpll6		1	BCM_SR_GENPLL6_48_USB_CLK



    lcpll0		crystal		0	BCM_SR_LCPLL0

    clk_sata_refp 	lcpll0		1	BCM_SR_LCPLL0_SATA_REFP_CLK

    clk_sata_refn	lcpll0		2	BCM_SR_LCPLL0_SATA_REFN_CLK

    clk_usb_ref		lcpll0		3	BCM_SR_LCPLL0_USB_REF_CLK

    sata_refpn		lcpll0		3	BCM_SR_LCPLL0_SATA_REFPN_CLK

    clk_sata_350	lcpll0		3	BCM_SR_LCPLL0_SATA_350_CLK

    clk_sata_500	lcpll0		4	BCM_SR_LCPLL0_SATA_500_CLK



    lcpll1		crystal		0	BCM_SR_LCPLL1

    wan 		lcpll1		1	BCM_SR_LCPLL0_WAN_CLK

    clk_wan		lcpll1		1	BCM_SR_LCPLL1_WAN_CLK

    clk_usb_ref		lcpll1		2	BCM_SR_LCPLL1_USB_REF_CLK

    clk_crmu_ts		lcpll1		3	BCM_SR_LCPLL1_CRMU_TS_CLK



    lcpll_pcie		crystal		0	BCM_SR_LCPLL_PCIE

    pcie_phy_ref 	lcpll1		1	BCM_SR_LCPLL_PCIE_PHY_REF_CLK
 
    clk_pcie_phy_ref	lcpll1		1	BCM_SR_LCPLL_PCIE_PHY_REF_CLK

drivers/clk/bcm/clk-bcm2835.c

+6 −7
Original line number Diff line number Diff line
@@ -1390,7 +1390,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 
	struct bcm2835_clock *clock;

	struct clk_init_data init;

	const char *parents[1 << CM_SRC_BITS];

	size_t i, j;

	size_t i;

	int ret;



	/*
@@ -1400,12 +1400,11 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 
	for (i = 0; i < data->num_mux_parents; i++) {

		parents[i] = data->parents[i];



		for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) {

			if (strcmp(parents[i], cprman_parent_names[j]) == 0) {

				parents[i] = cprman->real_parent_names[j];

				break;

			}

		}

		ret = match_string(cprman_parent_names,

				   ARRAY_SIZE(cprman_parent_names),

				   parents[i]);

		if (ret >= 0)

			parents[i] = cprman->real_parent_names[ret];

	}



	memset(&init, 0, sizeof(init));

drivers/clk/bcm/clk-sr.c

+120 −15
Original line number Diff line number Diff line
@@ -56,8 +56,8 @@ static const struct iproc_pll_ctrl sr_genpll0 = { 
};



static const struct iproc_clk_ctrl sr_genpll0_clk[] = {

	[BCM_SR_GENPLL0_SATA_CLK] = {

		.channel = BCM_SR_GENPLL0_SATA_CLK,

	[BCM_SR_GENPLL0_125M_CLK] = {

		.channel = BCM_SR_GENPLL0_125M_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 6, 0, 12),

		.mdiv = REG_VAL(0x18, 0, 9),
@@ -102,6 +102,65 @@ static int sr_genpll0_clk_init(struct platform_device *pdev) 
	return 0;

}



static const struct iproc_pll_ctrl sr_genpll2 = {

	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |

		IPROC_CLK_PLL_NEEDS_SW_CFG,

	.aon = AON_VAL(0x0, 1, 13, 12),

	.reset = RESET_VAL(0x0, 12, 11),

	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),

	.sw_ctrl = SW_CTRL_VAL(0x10, 31),

	.ndiv_int = REG_VAL(0x10, 20, 10),

	.ndiv_frac = REG_VAL(0x10, 0, 20),

	.pdiv = REG_VAL(0x14, 0, 4),

	.status = REG_VAL(0x30, 12, 1),

};



static const struct iproc_clk_ctrl sr_genpll2_clk[] = {

	[BCM_SR_GENPLL2_NIC_CLK] = {

		.channel = BCM_SR_GENPLL2_NIC_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 6, 0, 12),

		.mdiv = REG_VAL(0x18, 0, 9),

	},

	[BCM_SR_GENPLL2_TS_500_CLK] = {

		.channel = BCM_SR_GENPLL2_TS_500_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 7, 1, 13),

		.mdiv = REG_VAL(0x18, 10, 9),

	},

	[BCM_SR_GENPLL2_125_NITRO_CLK] = {

		.channel = BCM_SR_GENPLL2_125_NITRO_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 8, 2, 14),

		.mdiv = REG_VAL(0x18, 20, 9),

	},

	[BCM_SR_GENPLL2_CHIMP_CLK] = {

		.channel = BCM_SR_GENPLL2_CHIMP_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 9, 3, 15),

		.mdiv = REG_VAL(0x1c, 0, 9),

	},

	[BCM_SR_GENPLL2_NIC_FLASH_CLK] = {

		.channel = BCM_SR_GENPLL2_NIC_FLASH_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 10, 4, 16),

		.mdiv = REG_VAL(0x1c, 10, 9),

	},

	[BCM_SR_GENPLL2_FS4_CLK] = {

		.channel = BCM_SR_GENPLL2_FS4_CLK,

		.enable = ENABLE_VAL(0x4, 11, 5, 17),

		.mdiv = REG_VAL(0x1c, 20, 9),

	},

};



static int sr_genpll2_clk_init(struct platform_device *pdev)

{

	iproc_pll_clk_setup(pdev->dev.of_node,

			    &sr_genpll2, NULL, 0, sr_genpll2_clk,

			    ARRAY_SIZE(sr_genpll2_clk));

	return 0;

}



static const struct iproc_pll_ctrl sr_genpll3 = {

	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |

		IPROC_CLK_PLL_NEEDS_SW_CFG,
@@ -157,6 +216,30 @@ static const struct iproc_clk_ctrl sr_genpll4_clk[] = { 
		.enable = ENABLE_VAL(0x4, 6, 0, 12),

		.mdiv = REG_VAL(0x18, 0, 9),

	},

	[BCM_SR_GENPLL4_TPIU_PLL_CLK] = {

		.channel = BCM_SR_GENPLL4_TPIU_PLL_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 7, 1, 13),

		.mdiv = REG_VAL(0x18, 10, 9),

	},

	[BCM_SR_GENPLL4_NOC_CLK] = {

		.channel = BCM_SR_GENPLL4_NOC_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 8, 2, 14),

		.mdiv = REG_VAL(0x18, 20, 9),

	},

	[BCM_SR_GENPLL4_CHCLK_FS4_CLK] = {

		.channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 9, 3, 15),

		.mdiv = REG_VAL(0x1c, 0, 9),

	},

	[BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK] = {

		.channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 10, 4, 16),

		.mdiv = REG_VAL(0x1c, 10, 9),

	},

};



static int sr_genpll4_clk_init(struct platform_device *pdev)
@@ -181,18 +264,21 @@ static const struct iproc_pll_ctrl sr_genpll5 = { 
};



static const struct iproc_clk_ctrl sr_genpll5_clk[] = {

	[BCM_SR_GENPLL5_FS_CLK] = {

		.channel = BCM_SR_GENPLL5_FS_CLK,

		.flags = IPROC_CLK_AON,

	[BCM_SR_GENPLL5_FS4_HF_CLK] = {

		.channel = BCM_SR_GENPLL5_FS4_HF_CLK,

		.enable = ENABLE_VAL(0x4, 6, 0, 12),

		.mdiv = REG_VAL(0x18, 0, 9),

	},

	[BCM_SR_GENPLL5_SPU_CLK] = {

		.channel = BCM_SR_GENPLL5_SPU_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x4, 6, 0, 12),

	[BCM_SR_GENPLL5_CRYPTO_AE_CLK] = {

		.channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK,

		.enable = ENABLE_VAL(0x4, 7, 1, 12),

		.mdiv = REG_VAL(0x18, 10, 9),

	},

	[BCM_SR_GENPLL5_RAID_AE_CLK] = {

		.channel = BCM_SR_GENPLL5_RAID_AE_CLK,

		.enable = ENABLE_VAL(0x4, 8, 2, 14),

		.mdiv = REG_VAL(0x18, 20, 9),

	},

};



static int sr_genpll5_clk_init(struct platform_device *pdev)
@@ -214,24 +300,30 @@ static const struct iproc_pll_ctrl sr_lcpll0 = { 
};



static const struct iproc_clk_ctrl sr_lcpll0_clk[] = {

	[BCM_SR_LCPLL0_SATA_REF_CLK] = {

		.channel = BCM_SR_LCPLL0_SATA_REF_CLK,

	[BCM_SR_LCPLL0_SATA_REFP_CLK] = {

		.channel = BCM_SR_LCPLL0_SATA_REFP_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x0, 7, 1, 13),

		.mdiv = REG_VAL(0x14, 0, 9),

	},

	[BCM_SR_LCPLL0_USB_REF_CLK] = {

		.channel = BCM_SR_LCPLL0_USB_REF_CLK,

	[BCM_SR_LCPLL0_SATA_REFN_CLK] = {

		.channel = BCM_SR_LCPLL0_SATA_REFN_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x0, 8, 2, 14),

		.mdiv = REG_VAL(0x14, 10, 9),

	},

	[BCM_SR_LCPLL0_SATA_REFPN_CLK] = {

		.channel = BCM_SR_LCPLL0_SATA_REFPN_CLK,

	[BCM_SR_LCPLL0_SATA_350_CLK] = {

		.channel = BCM_SR_LCPLL0_SATA_350_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x0, 9, 3, 15),

		.mdiv = REG_VAL(0x14, 20, 9),

	},

	[BCM_SR_LCPLL0_SATA_500_CLK] = {

		.channel = BCM_SR_LCPLL0_SATA_500_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x0, 10, 4, 16),

		.mdiv = REG_VAL(0x18, 0, 9),

	},

};



static int sr_lcpll0_clk_init(struct platform_device *pdev)
@@ -259,6 +351,18 @@ static const struct iproc_clk_ctrl sr_lcpll1_clk[] = { 
		.enable = ENABLE_VAL(0x0, 7, 1, 13),

		.mdiv = REG_VAL(0x14, 0, 9),

	},

	[BCM_SR_LCPLL1_USB_REF_CLK] = {

		.channel = BCM_SR_LCPLL1_USB_REF_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x0, 8, 2, 14),

		.mdiv = REG_VAL(0x14, 10, 9),

	},

	[BCM_SR_LCPLL1_CRMU_TS_CLK] = {

		.channel = BCM_SR_LCPLL1_CRMU_TS_CLK,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x0, 9, 3, 15),

		.mdiv = REG_VAL(0x14, 20, 9),

	},

};



static int sr_lcpll1_clk_init(struct platform_device *pdev)
@@ -298,6 +402,7 @@ static int sr_lcpll_pcie_clk_init(struct platform_device *pdev) 


static const struct of_device_id sr_clk_dt_ids[] = {

	{ .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },

	{ .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },

	{ .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },

	{ .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },

	{ .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },

drivers/clk/clk-si544.c

+1 −0
Original line number Diff line number Diff line
@@ -207,6 +207,7 @@ static int si544_calc_muldiv(struct clk_si544_muldiv *settings, 


	/* And the fractional bits using the remainder */

	vco = (u64)tmp << 32;

	vco += FXO / 2; /* Round to nearest multiple */

	do_div(vco, FXO);

	settings->fb_div_frac = vco;

drivers/clk/clk.c

+2 −6
Original line number Diff line number Diff line
@@ -2175,7 +2175,6 @@ void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent) 
bool clk_has_parent(struct clk *clk, struct clk *parent)

{

	struct clk_core *core, *parent_core;

	unsigned int i;



	/* NULL clocks should be nops, so return success if either is NULL. */

	if (!clk || !parent)
@@ -2188,11 +2187,8 @@ bool clk_has_parent(struct clk *clk, struct clk *parent) 
	if (core->parent == parent_core)

		return true;



	for (i = 0; i < core->num_parents; i++)

		if (strcmp(core->parent_names[i], parent_core->name) == 0)

			return true;



	return false;

	return match_string(core->parent_names, core->num_parents,

			    parent_core->name) >= 0;

}

EXPORT_SYMBOL_GPL(clk_has_parent);

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