Commit 4d3f36c5 authored May 31, 2018 by Mike Looijmans Committed by Stephen Boyd Jun 01, 2018

clk-si544: Properly round requested frequency to nearest match



The si544 driver had a rounding problem that using the result of clk_round_rate
may set the clock to yet another rate, for example:
clk_round_rate(195000000) = 194999999
clk_round_rate(194999999) = 194999998

Clients would expect that after clk_set_rate(clk, freq2=clk_round_rate(clk, freq)) the
chip will be running at exactly freq2.

The problem was in the calculation of the feedback divider, it was always rounded
down instead of to the nearest possible VCO value.

After this change, the following holds true for any supported frequency:
actual_freq = clk_round_rate(clk, freq);
clk_set_rate(clk, actual_freq);
clk_round_rate(clk, actual_freq) == actual_freq && clk_get_rate(clk) == actual_freq

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Fixes: 953cc3e8 ("clk: Add driver for the si544 clock generator chip")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent 60cc43fc

drivers/clk/clk-si544.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -207,6 +207,7 @@ static int si544_calc_muldiv(struct clk_si544_muldiv *settings,

		/* And the fractional bits using the remainder */
		vco = (u64)tmp << 32;
		vco += FXO / 2; /* Round to nearest multiple */
		do_div(vco, FXO);
		settings->fb_div_frac = vco;

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