Commit 6ee3d385 authored May 20, 2018 by Paul Cercueil Committed by Stephen Boyd Jun 01, 2018

clk: ingenic: jz4770: Add 150us delay after enabling VPU clock



This is required, as we must not use the AHB1 bus before it is stable.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

parent a6523b6f

drivers/clk/ingenic/jz4770-cgu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
		[JZ4770_CLK_VPU] = {
		"vpu", CGU_CLK_GATE,
		.parents = { JZ4770_CLK_H1CLK, },
		.gate = { CGU_REG_LCR, 30 },
		.gate = { CGU_REG_LCR, 30, false, 150 },
		},
		[JZ4770_CLK_MMC0] = {
		"mmc0", CGU_CLK_GATE,

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