Merge branches 'clk-phase-errors', 'clk-amlogic', 'clk-renesas' and 'clk-allwinner' into clk-next

* Renesas Clock Pulse Generator / Module Standby and Software Reset

On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)

and MSSR (Module Standby and Software Reset) blocks are intimately connected,

and share the same register block.

They provide the following functionalities:

  - The CPG block generates various core clocks,

  - The MSSR block provides two functions:

      1. Module Standby, providing a Clock Domain to control the clock supply

	 to individual SoC devices,

      2. Reset Control, to perform a software reset of individual SoC devices.

Required Properties:

  - compatible: Must be one of:

      - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)

      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)

      - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)

      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)

      - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)

      - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)

      - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)

      - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)

      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)

      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)

      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)

      - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)

      - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)

  - reg: Base address and length of the memory resource used by the CPG/MSSR

    block

  - clocks: References to external parent clocks, one entry for each entry in

    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,

		 r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,

		 r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,

		 r8a77980, r8a77990, r8a77995)

      - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,

		  r8a77970, r8a77980)

      - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,

		     r8a7793, r8a7794)

  - #clock-cells: Must be 2

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

	and a core clock reference, as defined in

	<dt-bindings/clock/*-cpg-mssr.h>.

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

	a module number, as defined in the datasheet.

  - #power-domain-cells: Must be 0

      - SoC devices that are part of the CPG/MSSR Clock Domain and can be

	power-managed through Module Standby should refer to the CPG device

	node in their "power-domains" property, as documented by the generic PM

	Domain bindings in

	Documentation/devicetree/bindings/power/power-domain.yaml.

  - #reset-cells: Must be 1

      - The single reset specifier cell must be the module number, as defined

	in the datasheet.

Examples

--------

  - CPG device node:

	cpg: clock-controller@e6150000 {

		compatible = "renesas,r8a7795-cpg-mssr";

		reg = <0 0xe6150000 0 0x1000>;

		clocks = <&extal_clk>, <&extalr_clk>;

		clock-names = "extal", "extalr";

		#clock-cells = <2>;

		#power-domain-cells = <0>;

		#reset-cells = <1>;

	};

  - CPG/MSSR Clock Domain member device node:

	scif2: serial@e6e88000 {

		compatible = "renesas,scif-r8a7795", "renesas,scif";

		reg = <0 0xe6e88000 0 64>;

		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cpg CPG_MOD 310>;

		clock-names = "fck";

		dmas = <&dmac1 0x13>, <&dmac1 0x12>;

		dma-names = "tx", "rx";

		power-domains = <&cpg>;

		resets = <&cpg 310>;

	};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Renesas Clock Pulse Generator / Module Standby and Software Reset

maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |

  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)

  and MSSR (Module Standby and Software Reset) blocks are intimately connected,

  and share the same register block.

  They provide the following functionalities:

    - The CPG block generates various core clocks,

    - The MSSR block provides two functions:

        1. Module Standby, providing a Clock Domain to control the clock supply

           to individual SoC devices,

        2. Reset Control, to perform a software reset of individual SoC devices.

properties:

  compatible:

    enum:

      - renesas,r7s9210-cpg-mssr  # RZ/A2

      - renesas,r8a7743-cpg-mssr  # RZ/G1M

      - renesas,r8a7744-cpg-mssr  # RZ/G1N

      - renesas,r8a7745-cpg-mssr  # RZ/G1E

      - renesas,r8a77470-cpg-mssr # RZ/G1C

      - renesas,r8a774a1-cpg-mssr # RZ/G2M

      - renesas,r8a774b1-cpg-mssr # RZ/G2N

      - renesas,r8a774c0-cpg-mssr # RZ/G2E

      - renesas,r8a7790-cpg-mssr  # R-Car H2

      - renesas,r8a7791-cpg-mssr  # R-Car M2-W

      - renesas,r8a7792-cpg-mssr  # R-Car V2H

      - renesas,r8a7793-cpg-mssr  # R-Car M2-N

      - renesas,r8a7794-cpg-mssr  # R-Car E2

      - renesas,r8a7795-cpg-mssr  # R-Car H3

      - renesas,r8a7796-cpg-mssr  # R-Car M3-W

      - renesas,r8a77961-cpg-mssr # R-Car M3-W+

      - renesas,r8a77965-cpg-mssr # R-Car M3-N

      - renesas,r8a77970-cpg-mssr # R-Car V3M

      - renesas,r8a77980-cpg-mssr # R-Car V3H

      - renesas,r8a77990-cpg-mssr # R-Car E3

      - renesas,r8a77995-cpg-mssr # R-Car D3

  reg:

    maxItems: 1

  clocks:

    minItems: 1

    maxItems: 2

  clock-names:

    minItems: 1

    maxItems: 2

    items:

      enum:

        - extal     # All

        - extalr    # Most R-Car Gen3 and RZ/G2

        - usb_extal # Most R-Car Gen2 and RZ/G1

  '#clock-cells':

    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/*-cpg-mssr.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the datasheet.

    const: 2

  '#power-domain-cells':

    description:

      SoC devices that are part of the CPG/MSSR Clock Domain and can be

      power-managed through Module Standby should refer to the CPG device node

      in their "power-domains" property, as documented by the generic PM Domain

      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

    const: 0

  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the datasheet.

    const: 1

if:

  not:

    properties:

      compatible:

        items:

          enum:

            - renesas,r7s9210-cpg-mssr

then:

  required:

    - '#reset-cells'

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'

additionalProperties: false

examples:

  - |

    cpg: clock-controller@e6150000 {

            compatible = "renesas,r8a7795-cpg-mssr";

            reg = <0xe6150000 0x1000>;

            clocks = <&extal_clk>, <&extalr_clk>;

            clock-names = "extal", "extalr";

            #clock-cells = <2>;

            #power-domain-cells = <0>;

            #reset-cells = <1>;

    };

- reg: offset and length of the USB 2.0 clock selector register block.

- clocks: A list of phandles and specifier pairs.

- clock-names: Name of the clocks.

 - The functional clock must be "ehci_ohci"

 - The functional clock of USB 2.0 host side must be "ehci_ohci"

 - The functional clock of HS-USB side must be "hs-usb-if"

 - The USB_EXTAL clock pin must be "usb_extal"

 - The USB_XTAL clock pin must be "usb_xtal"

- #clock-cells: Must be 0

- power-domains: A phandle and symbolic PM domain specifier.

                 See power/renesas,rcar-sysc.yaml.

- resets: A list of phandles and specifier pairs.

- reset-names: Name of the resets.

 - The reset of USB 2.0 host side must be "ehci_ohci"

 - The reset of HS-USB side must be "hs-usb-if"

Example (R-Car H3):

		compatible = "renesas,r8a7795-rcar-usb2-clock-sel",

			     "renesas,rcar-gen3-usb2-clock-sel";

		reg = <0 0xe6590630 0 0x02>;

		clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;

		clock-names = "ehci_ohci", "usb_extal", "usb_xtal";

		clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,

			 <&usb_extal>, <&usb_xtal>;

		clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";

		#clock-cells = <0>;

		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

		resets = <&cpg 703>, <&cpg 704>;

		reset-names = "ehci_ohci", "hs-usb-if";

	};

}

EXPORT_SYMBOL_GPL(clk_hw_get_rate);

static unsigned long __clk_get_accuracy(struct clk_core *core)

static unsigned long clk_core_get_accuracy_no_lock(struct clk_core *core)

{

	if (!core)

		return 0;

		__clk_recalc_accuracies(child);

}

static long clk_core_get_accuracy(struct clk_core *core)

static long clk_core_get_accuracy_recalc(struct clk_core *core)

{

	unsigned long accuracy;

	clk_prepare_lock();

	if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))

		__clk_recalc_accuracies(core);

	accuracy = __clk_get_accuracy(core);

	clk_prepare_unlock();

	return accuracy;

	return clk_core_get_accuracy_no_lock(core);

}

/**

 */

long clk_get_accuracy(struct clk *clk)

{

	long accuracy;

	if (!clk)

		return 0;

	return clk_core_get_accuracy(clk->core);

	clk_prepare_lock();

	accuracy = clk_core_get_accuracy_recalc(clk->core);

	clk_prepare_unlock();

	return accuracy;

}

EXPORT_SYMBOL_GPL(clk_get_accuracy);

		__clk_recalc_rates(child, msg);

}

static unsigned long clk_core_get_rate(struct clk_core *core)

static unsigned long clk_core_get_rate_recalc(struct clk_core *core)

{

	unsigned long rate;

	clk_prepare_lock();

	if (core && (core->flags & CLK_GET_RATE_NOCACHE))

		__clk_recalc_rates(core, 0);

	rate = clk_core_get_rate_nolock(core);

	clk_prepare_unlock();

	return rate;

	return clk_core_get_rate_nolock(core);

}

/**

 */

unsigned long clk_get_rate(struct clk *clk)

{

	unsigned long rate;

	if (!clk)

		return 0;

	return clk_core_get_rate(clk->core);

	clk_prepare_lock();

	rate = clk_core_get_rate_recalc(clk->core);

	clk_prepare_unlock();

	return rate;

}

EXPORT_SYMBOL_GPL(clk_get_rate);

{

	int ret;

	clk_prepare_lock();

	lockdep_assert_held(&prepare_lock);

	if (!core->ops->get_phase)

		return 0;

	/* Always try to update cached phase if possible */

	if (core->ops->get_phase)

		core->phase = core->ops->get_phase(core->hw);

	ret = core->phase;

	clk_prepare_unlock();

	ret = core->ops->get_phase(core->hw);

	if (ret >= 0)

		core->phase = ret;

	return ret;

}

 */

int clk_get_phase(struct clk *clk)

{

	int ret;

	if (!clk)

		return 0;

	return clk_core_get_phase(clk->core);

	clk_prepare_lock();

	ret = clk_core_get_phase(clk->core);

	clk_prepare_unlock();

	return ret;

}

EXPORT_SYMBOL_GPL(clk_get_phase);

static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,

				 int level)

{

	seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",

	int phase;

	seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu ",

		   level * 3 + 1, "",

		   30 - level * 3, c->name,

		   c->enable_count, c->prepare_count, c->protect_count,

		   clk_core_get_rate(c), clk_core_get_accuracy(c),

		   clk_core_get_phase(c),

		   clk_core_get_scaled_duty_cycle(c, 100000));

		   clk_core_get_rate_recalc(c),

		   clk_core_get_accuracy_recalc(c));

	phase = clk_core_get_phase(c);

	if (phase >= 0)

		seq_printf(s, "%5d", phase);

	else

		seq_puts(s, "-----");

	seq_printf(s, " %6d\n", clk_core_get_scaled_duty_cycle(c, 100000));

}

static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,

static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)

{

	int phase;

	unsigned long min_rate, max_rate;

	clk_core_get_boundaries(c, &min_rate, &max_rate);

	seq_printf(s, "\"enable_count\": %d,", c->enable_count);

	seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);

	seq_printf(s, "\"protect_count\": %d,", c->protect_count);

	seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));

	seq_printf(s, "\"rate\": %lu,", clk_core_get_rate_recalc(c));

	seq_printf(s, "\"min_rate\": %lu,", min_rate);

	seq_printf(s, "\"max_rate\": %lu,", max_rate);

	seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));

	seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));

	seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy_recalc(c));

	phase = clk_core_get_phase(c);

	if (phase >= 0)

		seq_printf(s, "\"phase\": %d,", phase);

	seq_printf(s, "\"duty_cycle\": %u",

		   clk_core_get_scaled_duty_cycle(c, 100000));

}

static int __clk_core_init(struct clk_core *core)

{

	int ret;

	struct clk_core *parent;

	unsigned long rate;

	int phase;

	if (!core)

		return -EINVAL;

			goto out;

	}

	core->parent = __clk_init_parent(core);

	parent = core->parent = __clk_init_parent(core);

	/*

	 * Populate core->parent if parent has already been clk_core_init'd. If

	 * clocks and re-parent any that are children of the clock currently

	 * being clk_init'd.

	 */

	if (core->parent) {

		hlist_add_head(&core->child_node,

				&core->parent->children);

		core->orphan = core->parent->orphan;

	if (parent) {

		hlist_add_head(&core->child_node, &parent->children);

		core->orphan = parent->orphan;

	} else if (!core->num_parents) {

		hlist_add_head(&core->child_node, &clk_root_list);

		core->orphan = false;

	 */

	if (core->ops->recalc_accuracy)

		core->accuracy = core->ops->recalc_accuracy(core->hw,

					__clk_get_accuracy(core->parent));

	else if (core->parent)

		core->accuracy = core->parent->accuracy;

					clk_core_get_accuracy_no_lock(parent));

	else if (parent)

		core->accuracy = parent->accuracy;

	else

		core->accuracy = 0;

	/*

	 * Set clk's phase.

	 * Set clk's phase by clk_core_get_phase() caching the phase.

	 * Since a phase is by definition relative to its parent, just

	 * query the current clock phase, or just assume it's in phase.

	 */

	if (core->ops->get_phase)

		core->phase = core->ops->get_phase(core->hw);

	else

		core->phase = 0;

	phase = clk_core_get_phase(core);

	if (phase < 0) {

		ret = phase;

		pr_warn("%s: Failed to get phase for clk '%s'\n", __func__,

			core->name);

		goto out;

	}

	/*

	 * Set clk's duty cycle.

	 */

	if (core->ops->recalc_rate)

		rate = core->ops->recalc_rate(core->hw,

				clk_core_get_rate_nolock(core->parent));

	else if (core->parent)

		rate = core->parent->rate;

				clk_core_get_rate_nolock(parent));

	else if (parent)

		rate = parent->rate;

	else

		rate = 0;

	core->rate = core->req_rate = rate;

	},

};

/* SPICC SCLK source clock */

static const struct clk_parent_data spicc_sclk_parent_data[] = {

	{ .fw_name = "xtal", },

	{ .hw = &g12a_clk81.hw },

	{ .hw = &g12a_fclk_div4.hw },

	{ .hw = &g12a_fclk_div3.hw },

	{ .hw = &g12a_fclk_div5.hw },

	{ .hw = &g12a_fclk_div7.hw },

};

static struct clk_regmap g12a_spicc0_sclk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.mask = 7,

		.shift = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = spicc_sclk_parent_data,

		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),

	},

};

static struct clk_regmap g12a_spicc0_sclk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.shift = 0,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc0_sclk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};

static struct clk_regmap g12a_spicc0_sclk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.bit_idx = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc0_sclk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};

static struct clk_regmap g12a_spicc1_sclk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.mask = 7,

		.shift = 23,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = spicc_sclk_parent_data,

		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),

	},

};

static struct clk_regmap g12a_spicc1_sclk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.shift = 16,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc1_sclk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};

static struct clk_regmap g12a_spicc1_sclk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.bit_idx = 22,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc1_sclk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};

#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)

		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,

		[CLKID_TS_DIV]			= &g12a_ts_div.hw,

		[CLKID_TS]			= &g12a_ts.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

		[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,

		[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,

		[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,

		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,

		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,

	&sm1_cpu1_clk,

	&sm1_cpu2_clk,

	&sm1_cpu3_clk,

	&g12a_spicc0_sclk_sel,

	&g12a_spicc0_sclk_div,

	&g12a_spicc0_sclk,

	&g12a_spicc1_sclk_sel,

	&g12a_spicc1_sclk_div,

	&g12a_spicc1_sclk,

};

static const struct reg_sequence g12a_init_regs[] = {