Commit f58272b6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.7-tag2' of... 

Merge tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

  - Improved clock/reset handling for the R-Car USB2 Clock Selector
  - Conversion to json-schema of the Renesas CPG/MSSR DT bindings

* tag 'clk-renesas-for-v5.7-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
  clk: renesas: rcar-usb2-clock-sel: Add reset_control
  clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
parents 23b6bc70 eeb40fda

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

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* Renesas Clock Pulse Generator / Module Standby and Software Reset



On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)

and MSSR (Module Standby and Software Reset) blocks are intimately connected,

and share the same register block.



They provide the following functionalities:

  - The CPG block generates various core clocks,

  - The MSSR block provides two functions:

      1. Module Standby, providing a Clock Domain to control the clock supply

	 to individual SoC devices,

      2. Reset Control, to perform a software reset of individual SoC devices.



Required Properties:

  - compatible: Must be one of:

      - "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)

      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)

      - "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)

      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)

      - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)

      - "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)

      - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)

      - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)

      - "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)

      - "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)

      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)

      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)

      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)

      - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)

      - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)



  - reg: Base address and length of the memory resource used by the CPG/MSSR

    block



  - clocks: References to external parent clocks, one entry for each entry in

    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,

		 r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,

		 r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,

		 r8a77980, r8a77990, r8a77995)

      - "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,

		  r8a77970, r8a77980)

      - "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,

		     r8a7793, r8a7794)



  - #clock-cells: Must be 2

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

	and a core clock reference, as defined in

	<dt-bindings/clock/*-cpg-mssr.h>.

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

	a module number, as defined in the datasheet.



  - #power-domain-cells: Must be 0

      - SoC devices that are part of the CPG/MSSR Clock Domain and can be

	power-managed through Module Standby should refer to the CPG device

	node in their "power-domains" property, as documented by the generic PM

	Domain bindings in

	Documentation/devicetree/bindings/power/power-domain.yaml.



  - #reset-cells: Must be 1

      - The single reset specifier cell must be the module number, as defined

	in the datasheet.





Examples

--------



  - CPG device node:



	cpg: clock-controller@e6150000 {

		compatible = "renesas,r8a7795-cpg-mssr";

		reg = <0 0xe6150000 0 0x1000>;

		clocks = <&extal_clk>, <&extalr_clk>;

		clock-names = "extal", "extalr";

		#clock-cells = <2>;

		#power-domain-cells = <0>;

		#reset-cells = <1>;

	};





  - CPG/MSSR Clock Domain member device node:



	scif2: serial@e6e88000 {

		compatible = "renesas,scif-r8a7795", "renesas,scif";

		reg = <0 0xe6e88000 0 64>;

		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cpg CPG_MOD 310>;

		clock-names = "fck";

		dmas = <&dmac1 0x13>, <&dmac1 0x12>;

		dma-names = "tx", "rx";

		power-domains = <&cpg>;

		resets = <&cpg 310>;

	};

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas Clock Pulse Generator / Module Standby and Software Reset



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)

  and MSSR (Module Standby and Software Reset) blocks are intimately connected,

  and share the same register block.



  They provide the following functionalities:

    - The CPG block generates various core clocks,

    - The MSSR block provides two functions:

        1. Module Standby, providing a Clock Domain to control the clock supply

           to individual SoC devices,

        2. Reset Control, to perform a software reset of individual SoC devices.



properties:

  compatible:

    enum:

      - renesas,r7s9210-cpg-mssr  # RZ/A2

      - renesas,r8a7743-cpg-mssr  # RZ/G1M

      - renesas,r8a7744-cpg-mssr  # RZ/G1N

      - renesas,r8a7745-cpg-mssr  # RZ/G1E

      - renesas,r8a77470-cpg-mssr # RZ/G1C

      - renesas,r8a774a1-cpg-mssr # RZ/G2M

      - renesas,r8a774b1-cpg-mssr # RZ/G2N

      - renesas,r8a774c0-cpg-mssr # RZ/G2E

      - renesas,r8a7790-cpg-mssr  # R-Car H2

      - renesas,r8a7791-cpg-mssr  # R-Car M2-W

      - renesas,r8a7792-cpg-mssr  # R-Car V2H

      - renesas,r8a7793-cpg-mssr  # R-Car M2-N

      - renesas,r8a7794-cpg-mssr  # R-Car E2

      - renesas,r8a7795-cpg-mssr  # R-Car H3

      - renesas,r8a7796-cpg-mssr  # R-Car M3-W

      - renesas,r8a77961-cpg-mssr # R-Car M3-W+

      - renesas,r8a77965-cpg-mssr # R-Car M3-N

      - renesas,r8a77970-cpg-mssr # R-Car V3M

      - renesas,r8a77980-cpg-mssr # R-Car V3H

      - renesas,r8a77990-cpg-mssr # R-Car E3

      - renesas,r8a77995-cpg-mssr # R-Car D3



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



  clock-names:

    minItems: 1

    maxItems: 2

    items:

      enum:

        - extal     # All

        - extalr    # Most R-Car Gen3 and RZ/G2

        - usb_extal # Most R-Car Gen2 and RZ/G1



  '#clock-cells':

    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/*-cpg-mssr.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the datasheet.

    const: 2



  '#power-domain-cells':

    description:

      SoC devices that are part of the CPG/MSSR Clock Domain and can be

      power-managed through Module Standby should refer to the CPG device node

      in their "power-domains" property, as documented by the generic PM Domain

      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

    const: 0



  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the datasheet.

    const: 1



if:

  not:

    properties:

      compatible:

        items:

          enum:

            - renesas,r7s9210-cpg-mssr

then:

  required:

    - '#reset-cells'



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    cpg: clock-controller@e6150000 {

            compatible = "renesas,r8a7795-cpg-mssr";

            reg = <0xe6150000 0x1000>;

            clocks = <&extal_clk>, <&extalr_clk>;

            clock-names = "extal", "extalr";

            #clock-cells = <2>;

            #power-domain-cells = <0>;

            #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.txt

+14 −3
Original line number Diff line number Diff line
@@ -38,10 +38,17 @@ Required properties: 
- reg: offset and length of the USB 2.0 clock selector register block.

- clocks: A list of phandles and specifier pairs.

- clock-names: Name of the clocks.

 - The functional clock must be "ehci_ohci"

 - The functional clock of USB 2.0 host side must be "ehci_ohci"

 - The functional clock of HS-USB side must be "hs-usb-if"

 - The USB_EXTAL clock pin must be "usb_extal"

 - The USB_XTAL clock pin must be "usb_xtal"

- #clock-cells: Must be 0

- power-domains: A phandle and symbolic PM domain specifier.

                 See power/renesas,rcar-sysc.yaml.

- resets: A list of phandles and specifier pairs.

- reset-names: Name of the resets.

 - The reset of USB 2.0 host side must be "ehci_ohci"

 - The reset of HS-USB side must be "hs-usb-if"



Example (R-Car H3):
@@ -49,7 +56,11 @@ Example (R-Car H3): 
		compatible = "renesas,r8a7795-rcar-usb2-clock-sel",

			     "renesas,rcar-gen3-usb2-clock-sel";

		reg = <0 0xe6590630 0 0x02>;

		clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;

		clock-names = "ehci_ohci", "usb_extal", "usb_xtal";

		clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,

			 <&usb_extal>, <&usb_xtal>;

		clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";

		#clock-cells = <0>;

		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

		resets = <&cpg 703>, <&cpg 704>;

		reset-names = "ehci_ohci", "hs-usb-if";

	};

drivers/clk/renesas/Kconfig

+1 −0
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@@ -161,6 +161,7 @@ config CLK_RCAR_GEN3_CPG 
config CLK_RCAR_USB2_CLOCK_SEL

	bool "Renesas R-Car USB2 clock selector support"

	depends on ARCH_RENESAS || COMPILE_TEST

	select RESET_CONTROLLER

	help

	  This is a driver for R-Car USB2 clock selector

drivers/clk/renesas/rcar-usb2-clock-sel.c

+38 −2
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#include <linux/platform_device.h>

#include <linux/pm.h>

#include <linux/pm_runtime.h>

#include <linux/reset.h>

#include <linux/slab.h>



#define USB20_CLKSET0		0x00
@@ -26,9 +27,16 @@ 
#define CLKSET0_PRIVATE		BIT(0)

#define CLKSET0_EXTAL_ONLY	(CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)



static const struct clk_bulk_data rcar_usb2_clocks[] = {

	{ .id = "ehci_ohci", },

	{ .id = "hs-usb-if", },

};



struct usb2_clock_sel_priv {

	void __iomem *base;

	struct clk_hw hw;

	struct clk_bulk_data clks[ARRAY_SIZE(rcar_usb2_clocks)];

	struct reset_control *rsts;

	bool extal;

	bool xtal;

};
@@ -53,14 +61,32 @@ static void usb2_clock_sel_disable_extal_only(struct usb2_clock_sel_priv *priv) 


static int usb2_clock_sel_enable(struct clk_hw *hw)

{

	usb2_clock_sel_enable_extal_only(to_priv(hw));

	struct usb2_clock_sel_priv *priv = to_priv(hw);

	int ret;



	ret = reset_control_deassert(priv->rsts);

	if (ret)

		return ret;



	ret = clk_bulk_prepare_enable(ARRAY_SIZE(priv->clks), priv->clks);

	if (ret) {

		reset_control_assert(priv->rsts);

		return ret;

	}



	usb2_clock_sel_enable_extal_only(priv);



	return 0;

}



static void usb2_clock_sel_disable(struct clk_hw *hw)

{

	usb2_clock_sel_disable_extal_only(to_priv(hw));

	struct usb2_clock_sel_priv *priv = to_priv(hw);



	usb2_clock_sel_disable_extal_only(priv);



	clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clks), priv->clks);

	reset_control_assert(priv->rsts);

}



/*
@@ -119,6 +145,7 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev) 
	struct usb2_clock_sel_priv *priv;

	struct clk *clk;

	struct clk_init_data init;

	int ret;



	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);

	if (!priv)
@@ -128,6 +155,15 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev) 
	if (IS_ERR(priv->base))

		return PTR_ERR(priv->base);



	memcpy(priv->clks, rcar_usb2_clocks, sizeof(priv->clks));

	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(priv->clks), priv->clks);

	if (ret < 0)

		return ret;



	priv->rsts = devm_reset_control_array_get(dev, true, false);

	if (IS_ERR(priv->rsts))

		return PTR_ERR(priv->rsts);



	pm_runtime_enable(dev);

	pm_runtime_get_sync(dev);

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