Commit 23b6bc70 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.7-tag1' of... 

Merge tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add Crypto clocks on R-Car M3-W/W+, M3-N, E3, and D3
  - Add RPC (QSPI/HyperFLASH) clocks on R-Car H3, M3-W/W+, and M3-N

* tag 'clk-renesas-for-v5.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Remove use of ARCH_R8A7795
  clk: renesas: r8a77965: Add RPC clocks
  clk: renesas: r8a7796: Add RPC clocks
  clk: renesas: r8a7795: Add RPC clocks
  clk: renesas: rcar-gen3: Add CCREE clocks
parents bb6d3fb3 068e7f85

drivers/clk/renesas/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ config CLK_RENESAS 
	select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793

	select CLK_R8A7792 if ARCH_R8A7792

	select CLK_R8A7794 if ARCH_R8A7794

	select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 || ARCH_R8A7795

	select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951

	select CLK_R8A77960 if ARCH_R8A77960

	select CLK_R8A77961 if ARCH_R8A77961

	select CLK_R8A77965 if ARCH_R8A77965

drivers/clk/renesas/r8a7795-cpg-mssr.c

+8 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ enum clk_ids { 
	CLK_S3,

	CLK_SDSRC,

	CLK_SSPSRC,

	CLK_RPCSRC,

	CLK_RINT,



	/* Module Clocks */
@@ -70,6 +71,12 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),

	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),



	DEF_BASE("rpc",		R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,

		 CLK_RPCSRC),

	DEF_BASE("rpcd2",	R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,

		 R8A7795_CLK_RPC),



	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
@@ -242,6 +249,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("can-fd",		 914,	R8A7795_CLK_S3D2),

	DEF_MOD("can-if1",		 915,	R8A7795_CLK_S3D4),

	DEF_MOD("can-if0",		 916,	R8A7795_CLK_S3D4),

	DEF_MOD("rpc-if",		 917,	R8A7795_CLK_RPCD2),

	DEF_MOD("i2c6",			 918,	R8A7795_CLK_S0D6),

	DEF_MOD("i2c5",			 919,	R8A7795_CLK_S0D6),

	DEF_MOD("i2c-dvfs",		 926,	R8A7795_CLK_CP),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+10 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ enum clk_ids { 
	CLK_S3,

	CLK_SDSRC,

	CLK_SSPSRC,

	CLK_RPCSRC,

	CLK_RINT,



	/* Module Clocks */
@@ -72,6 +73,12 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),

	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),

	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),



	DEF_BASE("rpc",		R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,

		 CLK_RPCSRC),

	DEF_BASE("rpcd2",	R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,

		 R8A7796_CLK_RPC),



	DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
@@ -105,6 +112,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
	DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),



	DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cr",         R8A7796_CLK_CR,    CLK_PLL1_DIV4,  2, 1),

	DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",       R8A7796_CLK_CPEX,  CLK_EXTAL,      2, 1),
@@ -132,6 +140,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { 
	DEF_MOD("sys-dmac2",		 217,	R8A7796_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A7796_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A7796_CLK_S0D3),

	DEF_MOD("sceg-pub",		 229,	R8A7796_CLK_CR),

	DEF_MOD("cmt3",			 300,	R8A7796_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7796_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7796_CLK_R),
@@ -215,6 +224,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { 
	DEF_MOD("can-fd",		 914,	R8A7796_CLK_S3D2),

	DEF_MOD("can-if1",		 915,	R8A7796_CLK_S3D4),

	DEF_MOD("can-if0",		 916,	R8A7796_CLK_S3D4),

	DEF_MOD("rpc-if",		 917,	R8A7796_CLK_RPCD2),

	DEF_MOD("i2c6",			 918,	R8A7796_CLK_S0D6),

	DEF_MOD("i2c5",			 919,	R8A7796_CLK_S0D6),

	DEF_MOD("i2c-dvfs",		 926,	R8A7796_CLK_CP),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+11 −1
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ enum clk_ids { 
	CLK_S3,

	CLK_SDSRC,

	CLK_SSPSRC,

	CLK_RPCSRC,

	CLK_RINT,



	/* Module Clocks */
@@ -68,6 +69,12 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { 
	DEF_FIXED(".s2",	CLK_S2,			CLK_PLL1_DIV2,	4, 1),

	DEF_FIXED(".s3",	CLK_S3,			CLK_PLL1_DIV2,	6, 1),

	DEF_FIXED(".sdsrc",	CLK_SDSRC,		CLK_PLL1_DIV2,	2, 1),

	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),



	DEF_BASE("rpc",		R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,

		 CLK_RPCSRC),

	DEF_BASE("rpcd2",	R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,

		 R8A77965_CLK_RPC),



	DEF_GEN3_OSC(".r",	CLK_RINT,		CLK_EXTAL,	32),
@@ -100,6 +107,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { 
	DEF_GEN3_SD("sd3",	R8A77965_CLK_SD3,	CLK_SDSRC,	0x26c),



	DEF_FIXED("cl",		R8A77965_CLK_CL,	CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cr",         R8A77965_CLK_CR,	CLK_PLL1_DIV4,  2, 1),

	DEF_FIXED("cp",		R8A77965_CLK_CP,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cpex",	R8A77965_CLK_CPEX,	CLK_EXTAL,	2, 1),
@@ -127,6 +135,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 
	DEF_MOD("sys-dmac2",		217,	R8A77965_CLK_S3D1),

	DEF_MOD("sys-dmac1",		218,	R8A77965_CLK_S3D1),

	DEF_MOD("sys-dmac0",		219,	R8A77965_CLK_S0D3),

	DEF_MOD("sceg-pub",		229,	R8A77965_CLK_CR),



	DEF_MOD("cmt3",			300,	R8A77965_CLK_R),

	DEF_MOD("cmt2",			301,	R8A77965_CLK_R),
@@ -215,6 +224,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 
	DEF_MOD("can-fd",		914,	R8A77965_CLK_S3D2),

	DEF_MOD("can-if1",		915,	R8A77965_CLK_S3D4),

	DEF_MOD("can-if0",		916,	R8A77965_CLK_S3D4),

	DEF_MOD("rpc-if",		917,	R8A77965_CLK_RPCD2),

	DEF_MOD("i2c6",			918,	R8A77965_CLK_S0D6),

	DEF_MOD("i2c5",			919,	R8A77965_CLK_S0D6),

	DEF_MOD("i2c-dvfs",		926,	R8A77965_CLK_CP),

drivers/clk/renesas/r8a77990-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { 
	DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,	  0x026c),



	DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),

	DEF_FIXED("cr",        R8A77990_CLK_CR,    CLK_PLL1D2,     2, 1),

	DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
@@ -135,6 +136,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = { 
	DEF_MOD("sys-dmac2",		 217,	R8A77990_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A77990_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A77990_CLK_S3D1),

	DEF_MOD("sceg-pub",		 229,	R8A77990_CLK_CR),



	DEF_MOD("cmt3",			 300,	R8A77990_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A77990_CLK_R),

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