Commit dfbfee87 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Update audio clock gate hierarchy for meson8 and gxbb
 - Update g12a spicc clock sources

* tag 'clk-meson-v5.7-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: set audio output clock hierarchy
  clk: meson: g12a: add support for the SPICC SCLK Source clocks
  dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
  clk: meson: gxbb: set audio output clock hierarchy
  clk: meson: gxbb: add the gxl internal dac gate
  dt-bindings: clk: meson: add the gxl internal dac gate
parents bb6d3fb3 71202c41

drivers/clk/meson/g12a.c

+129 −0
Original line number Diff line number Diff line
@@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = { 
	},

};



/* SPICC SCLK source clock */



static const struct clk_parent_data spicc_sclk_parent_data[] = {

	{ .fw_name = "xtal", },

	{ .hw = &g12a_clk81.hw },

	{ .hw = &g12a_fclk_div4.hw },

	{ .hw = &g12a_fclk_div3.hw },

	{ .hw = &g12a_fclk_div5.hw },

	{ .hw = &g12a_fclk_div7.hw },

};



static struct clk_regmap g12a_spicc0_sclk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.mask = 7,

		.shift = 7,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = spicc_sclk_parent_data,

		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),

	},

};



static struct clk_regmap g12a_spicc0_sclk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.shift = 0,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc0_sclk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_spicc0_sclk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.bit_idx = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc0_sclk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc0_sclk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_spicc1_sclk_sel = {

	.data = &(struct clk_regmap_mux_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.mask = 7,

		.shift = 23,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = spicc_sclk_parent_data,

		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),

	},

};



static struct clk_regmap g12a_spicc1_sclk_div = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.shift = 16,

		.width = 6,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc1_sclk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap g12a_spicc1_sclk = {

	.data = &(struct clk_regmap_gate_data){

		.offset = HHI_SPICC_CLK_CNTL,

		.bit_idx = 22,

	},

	.hw.init = &(struct clk_init_data){

		.name = "spicc1_sclk",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&g12a_spicc1_sclk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
@@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = { 
		[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,

		[CLKID_TS_DIV]			= &g12a_ts_div.hw,

		[CLKID_TS]			= &g12a_ts.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = { 
		[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,

		[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,

		[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = { 
		[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,

		[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,

		[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,

		[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,

		[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,

		[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,

		[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,

		[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,

		[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,

		[NR_CLKS]			= NULL,

	},

	.num = NR_CLKS,
@@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&sm1_cpu1_clk,

	&sm1_cpu2_clk,

	&sm1_cpu3_clk,

	&g12a_spicc0_sclk_sel,

	&g12a_spicc0_sclk_div,

	&g12a_spicc0_sclk,

	&g12a_spicc1_sclk_sel,

	&g12a_spicc1_sclk_div,

	&g12a_spicc1_sclk,

};



static const struct reg_sequence g12a_init_regs[] = {

drivers/clk/meson/g12a.h

+5 −1
Original line number Diff line number Diff line
@@ -255,8 +255,12 @@ 
#define CLKID_DSU_CLK_DYN1			249

#define CLKID_DSU_CLK_DYN			250

#define CLKID_DSU_CLK_FINAL			251

#define CLKID_SPICC0_SCLK_SEL			256

#define CLKID_SPICC0_SCLK_DIV			257

#define CLKID_SPICC1_SCLK_SEL			259

#define CLKID_SPICC1_SCLK_DIV			260



#define NR_CLKS					256

#define NR_CLKS					262



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/g12a-clkc.h>

drivers/clk/meson/gxbb.c

+13 −8
Original line number Diff line number Diff line
@@ -2613,19 +2613,12 @@ static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 
static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);

static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);

static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);

static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);

static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);



static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);

static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);

static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);

static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);

static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);

static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);

static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);

static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);

static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);

static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);

static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);

static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);

static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);

static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
@@ -2680,6 +2673,16 @@ static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);

static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);



/* AIU gates */

static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);

static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);

static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);

static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);

static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);

static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);

static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);

static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);



/* Array of all clocks provided by this provider */



static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
@@ -3100,6 +3103,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { 
		[CLKID_HDMI_SEL]	    = &gxbb_hdmi_sel.hw,

		[CLKID_HDMI_DIV]	    = &gxbb_hdmi_div.hw,

		[CLKID_HDMI]		    = &gxbb_hdmi.hw,

		[CLKID_ACODEC]		    = &gxl_acodec.hw,

		[NR_CLKS]		    = NULL,

	},

	.num = NR_CLKS,
@@ -3491,6 +3495,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = { 
	&gxl_hdmi_pll_od,

	&gxl_hdmi_pll_od2,

	&gxl_hdmi_pll_dco,

	&gxl_acodec,

};



static const struct meson_eeclkc_data gxbb_clkc_data = {

drivers/clk/meson/gxbb.h

+1 −1
Original line number Diff line number Diff line
@@ -188,7 +188,7 @@ 
#define CLKID_HDMI_SEL		  203

#define CLKID_HDMI_DIV		  204



#define NR_CLKS			  206

#define NR_CLKS			  207



/* include the CLKIDs that have been made part of the DT binding */

#include <dt-bindings/clock/gxbb-clkc.h>

drivers/clk/meson/meson8b.c

+13 −8
Original line number Diff line number Diff line
@@ -2605,14 +2605,6 @@ static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30); 
static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);

static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);

static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);

static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);

static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);

static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);

static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);

static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);

static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);

static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);

static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);

static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);

static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);

static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
@@ -2659,6 +2651,19 @@ static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); 
static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);

static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);



/* AIU gates */

#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)



static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);

static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);

static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);

static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);

static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);

static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);

static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);

static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);



/* Always On (AO) domain gates */



static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);

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