iommu/vt-d: Handle non-page aligned address (288d08e7) · Commits · 戴 / test

Address information for device TLB invalidation comes from userspace when device is directly assigned to a guest with vIOMMU support. VT-d requires page aligned address. This patch checks and enforce address to be page aligned, otherwise reserved bits can be set in the invalidation descriptor. Unrecoverable fault will be reported due to non-zero value in the reserved bits. Fixes: ("iommu/vt-d: Support flushing more translation cache types") Signed-off-by:

Liu Yi L <yi.l.liu@intel.com> Signed-off-by:

Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by:

Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by:

Eric Auger <eric.auger@redhat.com> Link: https://lore.kernel.org/r/20200724014925.15523-5-baolu.lu@linux.intel.com Signed-off-by:

Joerg Roedel <jroedel@suse.de>

drivers/iommu/intel/dmar.c

+19 −2

Original line number	Diff line number	Diff line
		@@ -1456,9 +1456,26 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
		* Max Invs Pending (MIP) is set to 0 for now until we have DIT in
		* ECAP.
		*/
		desc.qw1 \|= addr & ~mask;
		if (size_order)
		if (addr & GENMASK_ULL(size_order + VTD_PAGE_SHIFT, 0))
		pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n",
		addr, size_order);

		/* Take page address */
		desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);

		if (size_order) {
		/*
		* Existing 0s in address below size_order may be the least
		* significant bit, we must set them to 1s to avoid having
		* smaller size than desired.
		*/
		desc.qw1 \|= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
		VTD_PAGE_SHIFT);
		/* Clear size_order bit to indicate size */
		desc.qw1 &= ~mask;
		/* Set the S bit to indicate flushing more than 1 page */
		desc.qw1 \|= QI_DEV_EIOTLB_SIZE;
		}

		qi_submit_sync(iommu, &desc, 1, 0);
		}

Admin message