Commit 61a06a16 authored by Jacob Pan's avatar Jacob Pan Committed by Joerg Roedel
Browse files

iommu/vt-d: Support flushing more translation cache types 



When Shared Virtual Memory is exposed to a guest via vIOMMU, scalable
IOTLB invalidation may be passed down from outside IOMMU subsystems.
This patch adds invalidation functions that can be used for additional
translation cache types.

Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200516062101.29541-6-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 56722a43

drivers/iommu/dmar.c

+39 −0
Original line number Diff line number Diff line
@@ -1421,6 +1421,45 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, 
	qi_submit_sync(&desc, iommu);

}



/* PASID-based device IOTLB Invalidate */

void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,

			      u32 pasid,  u16 qdep, u64 addr,

			      unsigned int size_order, u64 granu)

{

	unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);

	struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};



	desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |

		QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |

		QI_DEV_IOTLB_PFSID(pfsid);

	desc.qw1 = QI_DEV_EIOTLB_GLOB(granu);



	/*

	 * If S bit is 0, we only flush a single page. If S bit is set,

	 * The least significant zero bit indicates the invalidation address

	 * range. VT-d spec 6.5.2.6.

	 * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.

	 * size order = 0 is PAGE_SIZE 4KB

	 * Max Invs Pending (MIP) is set to 0 for now until we have DIT in

	 * ECAP.

	 */

	desc.qw1 |= addr & ~mask;

	if (size_order)

		desc.qw1 |= QI_DEV_EIOTLB_SIZE;



	qi_submit_sync(&desc, iommu);

}



void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did,

			  u64 granu, int pasid)

{

	struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};



	desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) |

			QI_PC_GRAN(granu) | QI_PC_TYPE;

	qi_submit_sync(&desc, iommu);

}



/*

 * Disable Queued Invalidation interface.

 */

drivers/iommu/intel-pasid.c

+2 −1
Original line number Diff line number Diff line
@@ -375,7 +375,8 @@ pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, 
{

	struct qi_desc desc;



	desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);

	desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) |

		QI_PC_PASID(pasid) | QI_PC_TYPE;

	desc.qw1 = 0;

	desc.qw2 = 0;

	desc.qw3 = 0;

include/linux/intel-iommu.h

+17 −4
Original line number Diff line number Diff line
@@ -334,7 +334,7 @@ enum { 
#define QI_IOTLB_GRAN(gran) 	(((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))

#define QI_IOTLB_ADDR(addr)	(((u64)addr) & VTD_PAGE_MASK)

#define QI_IOTLB_IH(ih)		(((u64)ih) << 6)

#define QI_IOTLB_AM(am)		(((u8)am))

#define QI_IOTLB_AM(am)		(((u8)am) & 0x3f)



#define QI_CC_FM(fm)		(((u64)fm) << 48)

#define QI_CC_SID(sid)		(((u64)sid) << 32)
@@ -353,16 +353,21 @@ enum { 
#define QI_PC_DID(did)		(((u64)did) << 16)

#define QI_PC_GRAN(gran)	(((u64)gran) << 4)



#define QI_PC_ALL_PASIDS	(QI_PC_TYPE | QI_PC_GRAN(0))

#define QI_PC_PASID_SEL		(QI_PC_TYPE | QI_PC_GRAN(1))

/* PASID cache invalidation granu */

#define QI_PC_ALL_PASIDS	0

#define QI_PC_PASID_SEL		1



#define QI_EIOTLB_ADDR(addr)	((u64)(addr) & VTD_PAGE_MASK)

#define QI_EIOTLB_IH(ih)	(((u64)ih) << 6)

#define QI_EIOTLB_AM(am)	(((u64)am))

#define QI_EIOTLB_AM(am)	(((u64)am) & 0x3f)

#define QI_EIOTLB_PASID(pasid) 	(((u64)pasid) << 32)

#define QI_EIOTLB_DID(did)	(((u64)did) << 16)

#define QI_EIOTLB_GRAN(gran) 	(((u64)gran) << 4)



/* QI Dev-IOTLB inv granu */

#define QI_DEV_IOTLB_GRAN_ALL		1

#define QI_DEV_IOTLB_GRAN_PASID_SEL	0



#define QI_DEV_EIOTLB_ADDR(a)	((u64)(a) & VTD_PAGE_MASK)

#define QI_DEV_EIOTLB_SIZE	(((u64)1) << 11)

#define QI_DEV_EIOTLB_GLOB(g)	((u64)g)
@@ -679,8 +684,16 @@ extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, 
			  unsigned int size_order, u64 type);

extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,

			u16 qdep, u64 addr, unsigned mask);



void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,

		     unsigned long npages, bool ih);



void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,

			      u32 pasid, u16 qdep, u64 addr,

			      unsigned int size_order, u64 granu);

void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,

			  int pasid);



extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);



extern int dmar_ir_support(void);

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