Commit e7e69461 authored Jul 24, 2020 by Jacob Pan Committed by Joerg Roedel Jul 24, 2020

iommu/vt-d: Fix PASID devTLB invalidation



DevTLB flush can be used for both DMA request with and without PASIDs.
The former uses PASID#0 (RID2PASID), latter uses non-zero PASID for SVA
usage.

This patch adds a check for PASID value such that devTLB flush with
PASID is used for SVA case. This is more efficient in that multiple
PASIDs can be used by a single device, when tearing down a PASID entry
we shall flush only the devTLB specific to a PASID.

Fixes: 6f7db75e ("iommu/vt-d: Add second level page table")
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200724014925.15523-4-baolu.lu@linux.intel.com


Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent 78df6c86

drivers/iommu/intel/pasid.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -486,7 +486,16 @@ devtlb_invalidation_with_pasid(struct intel_iommu *iommu,
		qdep = info->ats_qdep;
		pfsid = info->pfsid;

		/*
		* When PASID 0 is used, it indicates RID2PASID(DMA request w/o PASID),
		* devTLB flush w/o PASID should be used. For non-zero PASID under
		* SVA usage, device could do DMA with multiple PASIDs. It is more
		* efficient to flush devTLB specific to the PASID.
		*/
		if (pasid == PASID_RID2PASID)
		qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT);
		else
		qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT);
		}

		void intel_pasid_tear_down_entry(struct intel_iommu iommu, struct device dev,

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