Commit 78df6c86 authored by Jacob Pan's avatar Jacob Pan Committed by Joerg Roedel
Browse files

iommu/vt-d: Remove global page support in devTLB flush 



Global pages support is removed from VT-d spec 3.0 for dev TLB
invalidation. This patch is to remove the bits for vSVA. Similar change
already made for the native SVA. See the link below.

Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarEric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/linux-iommu/20190830142919.GE11578@8bytes.org/T/
Link: https://lore.kernel.org/r/20200724014925.15523-3-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 5f77d6ca

drivers/iommu/intel/dmar.c

+1 −3
Original line number Diff line number Diff line
@@ -1438,8 +1438,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, 


/* PASID-based device IOTLB Invalidate */

void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,

			      u32 pasid,  u16 qdep, u64 addr,

			      unsigned int size_order, u64 granu)

			      u32 pasid,  u16 qdep, u64 addr, unsigned int size_order)

{

	unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);

	struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
@@ -1447,7 +1446,6 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, 
	desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |

		QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |

		QI_DEV_IOTLB_PFSID(pfsid);

	desc.qw1 = QI_DEV_EIOTLB_GLOB(granu);



	/*

	 * If S bit is 0, we only flush a single page. If S bit is set,

drivers/iommu/intel/iommu.c

+2 −2
Original line number Diff line number Diff line
@@ -5474,7 +5474,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev, 
						info->pfsid, pasid,

						info->ats_qdep,

						inv_info->addr_info.addr,

						size, granu);

						size);

			break;

		case IOMMU_CACHE_INV_TYPE_DEV_IOTLB:

			if (info->ats_enabled)
@@ -5482,7 +5482,7 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev, 
						info->pfsid, pasid,

						info->ats_qdep,

						inv_info->addr_info.addr,

						size, granu);

						size);

			else

				pr_warn_ratelimited("Passdown device IOTLB flush w/o ATS!\n");

			break;

include/linux/intel-iommu.h

+1 −2
Original line number Diff line number Diff line
@@ -381,7 +381,6 @@ enum { 


#define QI_DEV_EIOTLB_ADDR(a)	((u64)(a) & VTD_PAGE_MASK)

#define QI_DEV_EIOTLB_SIZE	(((u64)1) << 11)

#define QI_DEV_EIOTLB_GLOB(g)	((u64)(g) & 0x1)

#define QI_DEV_EIOTLB_PASID(p)	((u64)((p) & 0xfffff) << 32)

#define QI_DEV_EIOTLB_SID(sid)	((u64)((sid) & 0xffff) << 16)

#define QI_DEV_EIOTLB_QDEP(qd)	((u64)((qd) & 0x1f) << 4)
@@ -705,7 +704,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, 


void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,

			      u32 pasid, u16 qdep, u64 addr,

			      unsigned int size_order, u64 granu);

			      unsigned int size_order);

void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,

			  int pasid);

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