Commit 18091360 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sunxi-dt-for-3.15' of https://github.com/mripard/linux into next/dt 

Allwinner DT patches for 3.15, take 1 from Maxime Ripard:
  - Add SPI controllers for all the SoCs
  - Add various missing aliases
  - Add USB clocks nodes
  - Addition of the GMAC support
  - Introduction of the pcDuino board
  - A few DT cleanup patches: change of compatibles,

* tag 'sunxi-dt-for-3.15' of https://github.com/mripard/linux

: (33 commits)
  ARM: sun6i: dt: Fix mod0 compatible
  ARM: dts: sun7i: Enable the SPI controllers of the A20-olinuxino-micro
  ARM: dt: sun7i: Add SPI muxing options
  ARM: dt: sun5i: Add A13 SPI controller nodes
  ARM: dt: sun5i: Add A10s SPI controller nodes
  ARM: dt: sun4i: Add A10 SPI controller nodes
  ARM: dt: sun7i: Add A20 SPI controller nodes
  ARM: sun4i: dt: Remove grouping + simple-bus compatible for regulators
  ARM: sunxi: dt: Convert to the new clock compatibles
  ARM: sun7i: add arch timer node
  ARM: sun7i: dt: Add bindings for USB clocks
  ARM: sun5i: dt: Add bindings for USB clocks
  ARM: sun4i: dt: Add bindings for USB clocks
  ARM: dts: sun7i: Add ethernet alias for GMAC
  ARM: dts: sun7i: a20-olinuxino-micro: Enable GMAC instead of EMAC
  ARM: dts: sun7i: cubieboard2: Enable GMAC instead of EMAC
  ARM: dts: sun7i: cubietruck: Enable the GMAC
  ARM: dts: sun7i: Add pin muxing options for the GMAC
  ARM: dts: sun7i: Add GMAC controller node to sun7i DTSI
  ARM: dts: sun7i: Add GMAC clock node to sun7i DTSI
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b989e36a 225b0216

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -322,6 +322,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \ 
	sun4i-a10-cubieboard.dtb \

	sun4i-a10-mini-xplus.dtb \

	sun4i-a10-hackberry.dtb \

	sun4i-a10-pcduino.dtb \

	sun5i-a10s-olinuxino-micro.dtb \

	sun5i-a13-olinuxino.dtb \

	sun5i-a13-olinuxino-micro.dtb \

arch/arm/boot/dts/sun4i-a10-a1000.dts

+9 −13
Original line number Diff line number Diff line
@@ -80,9 +80,6 @@ 
		};

	};



	regulators {

		compatible = "simple-bus";



	reg_emac_3v3: emac-3v3 {

		compatible = "regulator-fixed";

		pinctrl-names = "default";
@@ -94,4 +91,3 @@ 
		gpio = <&pio 7 15 0>;

	};

};
 
};

arch/arm/boot/dts/sun4i-a10-hackberry.dts

+7 −11
Original line number Diff line number Diff line
@@ -54,9 +54,6 @@ 
		};

	};



	regulators {

		compatible = "simple-bus";



	reg_emac_3v3: emac-3v3 {

		compatible = "regulator-fixed";

		regulator-name = "emac-3v3";
@@ -66,4 +63,3 @@ 
		gpio = <&pio 7 19 0>;

	};

};
 
};

arch/arm/boot/dts/sun4i-a10-pcduino.dts

0 → 100644
+48 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2014 Zoltan HERPAI

 * Zoltan HERPAI <wigyori@uid0.hu>

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



/dts-v1/;

/include/ "sun4i-a10.dtsi"



/ {

	model = "LinkSprite pcDuino";

	compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";



	soc@01c00000 {

		emac: ethernet@01c0b000 {

			pinctrl-names = "default";

			pinctrl-0 = <&emac_pins_a>;

			phy = <&phy1>;

			status = "okay";

		};



		mdio@01c0b080 {

			status = "okay";



			phy1: ethernet-phy@1 {

				reg = <1>;

			};

		};



		uart0: serial@01c28000 {

			pinctrl-names = "default";

			pinctrl-0 = <&uart0_pins_a>;

			status = "okay";

		};



		i2c0: i2c@01c2ac00 {

			pinctrl-names = "default";

			pinctrl-0 = <&i2c0_pins_a>;

			status = "okay";

		};

	};

};

arch/arm/boot/dts/sun4i-a10.dtsi

+109 −40
Original line number Diff line number Diff line
@@ -19,6 +19,12 @@ 
		ethernet0 = &emac;

		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &uart2;

		serial3 = &uart3;

		serial4 = &uart4;

		serial5 = &uart5;

		serial6 = &uart6;

		serial7 = &uart7;

	};



	cpus {
@@ -52,44 +58,48 @@ 
			clock-frequency = <0>;

		};



		osc24M: osc24M@01c20050 {

		osc24M: clk@01c20050 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-osc-clk";

			compatible = "allwinner,sun4i-a10-osc-clk";

			reg = <0x01c20050 0x4>;

			clock-frequency = <24000000>;

			clock-output-names = "osc24M";

		};



		osc32k: osc32k {

		osc32k: clk@0 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <32768>;

			clock-output-names = "osc32k";

		};



		pll1: pll1@01c20000 {

		pll1: clk@01c20000 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-pll1-clk";

			compatible = "allwinner,sun4i-a10-pll1-clk";

			reg = <0x01c20000 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll1";

		};



		pll4: pll4@01c20018 {

		pll4: clk@01c20018 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-pll1-clk";

			compatible = "allwinner,sun4i-a10-pll1-clk";

			reg = <0x01c20018 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll4";

		};



		pll5: pll5@01c20020 {

		pll5: clk@01c20020 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-pll5-clk";

			compatible = "allwinner,sun4i-a10-pll5-clk";

			reg = <0x01c20020 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll5_ddr", "pll5_other";

		};



		pll6: pll6@01c20028 {

		pll6: clk@01c20028 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-pll6-clk";

			compatible = "allwinner,sun4i-a10-pll6-clk";

			reg = <0x01c20028 0x4>;

			clocks = <&osc24M>;

			clock-output-names = "pll6_sata", "pll6_other", "pll6";
@@ -98,21 +108,23 @@ 
		/* dummy is 200M */

		cpu: cpu@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-cpu-clk";

			compatible = "allwinner,sun4i-a10-cpu-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;

			clock-output-names = "cpu";

		};



		axi: axi@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-axi-clk";

			compatible = "allwinner,sun4i-a10-axi-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&cpu>;

			clock-output-names = "axi";

		};



		axi_gates: axi_gates@01c2005c {

		axi_gates: clk@01c2005c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-axi-gates-clk";

			compatible = "allwinner,sun4i-a10-axi-gates-clk";

			reg = <0x01c2005c 0x4>;

			clocks = <&axi>;

			clock-output-names = "axi_dram";
@@ -120,14 +132,15 @@ 


		ahb: ahb@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-ahb-clk";

			compatible = "allwinner,sun4i-a10-ahb-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&axi>;

			clock-output-names = "ahb";

		};



		ahb_gates: ahb_gates@01c20060 {

		ahb_gates: clk@01c20060 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-ahb-gates-clk";

			compatible = "allwinner,sun4i-a10-ahb-gates-clk";

			reg = <0x01c20060 0x8>;

			clocks = <&ahb>;

			clock-output-names = "ahb_usb0", "ahb_ehci0",
@@ -145,14 +158,15 @@ 


		apb0: apb0@01c20054 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb0-clk";

			compatible = "allwinner,sun4i-a10-apb0-clk";

			reg = <0x01c20054 0x4>;

			clocks = <&ahb>;

			clock-output-names = "apb0";

		};



		apb0_gates: apb0_gates@01c20068 {

		apb0_gates: clk@01c20068 {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-apb0-gates-clk";

			compatible = "allwinner,sun4i-a10-apb0-gates-clk";

			reg = <0x01c20068 0x4>;

			clocks = <&apb0>;

			clock-output-names = "apb0_codec", "apb0_spdif",
@@ -162,21 +176,23 @@ 


		apb1_mux: apb1_mux@01c20058 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb1-mux-clk";

			compatible = "allwinner,sun4i-a10-apb1-mux-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;

			clock-output-names = "apb1_mux";

		};



		apb1: apb1@01c20058 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-apb1-clk";

			compatible = "allwinner,sun4i-a10-apb1-clk";

			reg = <0x01c20058 0x4>;

			clocks = <&apb1_mux>;

			clock-output-names = "apb1";

		};



		apb1_gates: apb1_gates@01c2006c {

		apb1_gates: clk@01c2006c {

			#clock-cells = <1>;

			compatible = "allwinner,sun4i-apb1-gates-clk";

			compatible = "allwinner,sun4i-a10-apb1-gates-clk";

			reg = <0x01c2006c 0x4>;

			clocks = <&apb1>;

			clock-output-names = "apb1_i2c0", "apb1_i2c1",
@@ -189,7 +205,7 @@ 


		nand_clk: clk@01c20080 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20080 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "nand";
@@ -197,7 +213,7 @@ 


		ms_clk: clk@01c20084 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20084 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ms";
@@ -205,7 +221,7 @@ 


		mmc0_clk: clk@01c20088 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20088 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc0";
@@ -213,7 +229,7 @@ 


		mmc1_clk: clk@01c2008c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c2008c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc1";
@@ -221,7 +237,7 @@ 


		mmc2_clk: clk@01c20090 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20090 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc2";
@@ -229,7 +245,7 @@ 


		mmc3_clk: clk@01c20094 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20094 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "mmc3";
@@ -237,7 +253,7 @@ 


		ts_clk: clk@01c20098 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c20098 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ts";
@@ -245,7 +261,7 @@ 


		ss_clk: clk@01c2009c {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c2009c 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ss";
@@ -253,7 +269,7 @@ 


		spi0_clk: clk@01c200a0 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200a0 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "spi0";
@@ -261,7 +277,7 @@ 


		spi1_clk: clk@01c200a4 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200a4 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "spi1";
@@ -269,7 +285,7 @@ 


		spi2_clk: clk@01c200a8 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200a8 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "spi2";
@@ -277,7 +293,7 @@ 


		pata_clk: clk@01c200ac {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200ac 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "pata";
@@ -285,7 +301,7 @@ 


		ir0_clk: clk@01c200b0 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200b0 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ir0";
@@ -293,15 +309,24 @@ 


		ir1_clk: clk@01c200b4 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200b4 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "ir1";

		};



		usb_clk: clk@01c200cc {

			#clock-cells = <1>;

		        #reset-cells = <1>;

			compatible = "allwinner,sun4i-a10-usb-clk";

			reg = <0x01c200cc 0x4>;

			clocks = <&pll6 1>;

			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";

		};



		spi3_clk: clk@01c200d4 {

			#clock-cells = <0>;

			compatible = "allwinner,sun4i-mod0-clk";

			compatible = "allwinner,sun4i-a10-mod0-clk";

			reg = <0x01c200d4 0x4>;

			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;

			clock-output-names = "spi3";
@@ -314,6 +339,28 @@ 
		#size-cells = <1>;

		ranges;



		spi0: spi@01c05000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c05000 0x1000>;

			interrupts = <10>;

			clocks = <&ahb_gates 20>, <&spi0_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi1: spi@01c06000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c06000 0x1000>;

			interrupts = <11>;

			clocks = <&ahb_gates 21>, <&spi1_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		emac: ethernet@01c0b000 {

			compatible = "allwinner,sun4i-a10-emac";

			reg = <0x01c0b000 0x1000>;
@@ -330,6 +377,28 @@ 
			#size-cells = <0>;

		};



		spi2: spi@01c17000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c17000 0x1000>;

			interrupts = <12>;

			clocks = <&ahb_gates 22>, <&spi2_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		spi3: spi@01c1f000 {

			compatible = "allwinner,sun4i-a10-spi";

			reg = <0x01c1f000 0x1000>;

			interrupts = <50>;

			clocks = <&ahb_gates 23>, <&spi3_clk>;

			clock-names = "ahb", "mod";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		intc: interrupt-controller@01c20400 {

			compatible = "allwinner,sun4i-ic";

			reg = <0x01c20400 0x400>;

CRA Git | Maintained and supported by SUSTech CRA and CCSE