Commit 225b0216 authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: sun6i: dt: Fix mod0 compatible



The module 0 clock compatibles were changed between the time the patch was sent
and it was merged. Update the compatibles.

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent d5cf89c9
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+4 −4
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi0";
@@ -208,7 +208,7 @@

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi1";
@@ -216,7 +216,7 @@

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi2";
@@ -224,7 +224,7 @@

		spi3_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-mod0-clk";
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi3";