Merge tag 'exynos-clk' of... (b989e36a) · Commits · 戴 / test

Documentation/devicetree/bindings/clock/exynos4-clock.txt

+6 −253

Original line number	Diff line number	Diff line
		@@ -15,259 +15,12 @@ Required Properties:

		- #clock-cells: should be 1.

		The following is the list of clocks generated by the controller. Each clock is
		assigned an identifier and client nodes use this identifier to specify the
		clock which they consume. Some of the clocks are available only on a particular
		Exynos4 SoC and this is specified where applicable.


		[Core Clocks]

		Clock ID SoC (if specific)
		-----------------------------------------------

		xxti 1
		xusbxti 2
		fin_pll 3
		fout_apll 4
		fout_mpll 5
		fout_epll 6
		fout_vpll 7
		sclk_apll 8
		sclk_mpll 9
		sclk_epll 10
		sclk_vpll 11
		arm_clk 12
		aclk200 13
		aclk100 14
		aclk160 15
		aclk133 16
		mout_mpll_user_t 17 Exynos4x12
		mout_mpll_user_c 18 Exynos4x12
		mout_core 19
		mout_apll 20


		[Clock Gate for Special Clocks]

		Clock ID SoC (if specific)
		-----------------------------------------------

		sclk_fimc0 128
		sclk_fimc1 129
		sclk_fimc2 130
		sclk_fimc3 131
		sclk_cam0 132
		sclk_cam1 133
		sclk_csis0 134
		sclk_csis1 135
		sclk_hdmi 136
		sclk_mixer 137
		sclk_dac 138
		sclk_pixel 139
		sclk_fimd0 140
		sclk_mdnie0 141 Exynos4412
		sclk_mdnie_pwm0 12 142 Exynos4412
		sclk_mipi0 143
		sclk_audio0 144
		sclk_mmc0 145
		sclk_mmc1 146
		sclk_mmc2 147
		sclk_mmc3 148
		sclk_mmc4 149
		sclk_sata 150 Exynos4210
		sclk_uart0 151
		sclk_uart1 152
		sclk_uart2 153
		sclk_uart3 154
		sclk_uart4 155
		sclk_audio1 156
		sclk_audio2 157
		sclk_spdif 158
		sclk_spi0 159
		sclk_spi1 160
		sclk_spi2 161
		sclk_slimbus 162
		sclk_fimd1 163 Exynos4210
		sclk_mipi1 164 Exynos4210
		sclk_pcm1 165
		sclk_pcm2 166
		sclk_i2s1 167
		sclk_i2s2 168
		sclk_mipihsi 169 Exynos4412
		sclk_mfc 170
		sclk_pcm0 171
		sclk_g3d 172
		sclk_pwm_isp 173 Exynos4x12
		sclk_spi0_isp 174 Exynos4x12
		sclk_spi1_isp 175 Exynos4x12
		sclk_uart_isp 176 Exynos4x12
		sclk_fimg2d 177

		[Peripheral Clock Gates]

		Clock ID SoC (if specific)
		-----------------------------------------------

		fimc0 256
		fimc1 257
		fimc2 258
		fimc3 259
		csis0 260
		csis1 261
		jpeg 262
		smmu_fimc0 263
		smmu_fimc1 264
		smmu_fimc2 265
		smmu_fimc3 266
		smmu_jpeg 267
		vp 268
		mixer 269
		tvenc 270 Exynos4210
		hdmi 271
		smmu_tv 272
		mfc 273
		smmu_mfcl 274
		smmu_mfcr 275
		g3d 276
		g2d 277
		rotator 278 Exynos4210
		mdma 279 Exynos4210
		smmu_g2d 280 Exynos4210
		smmu_rotator 281 Exynos4210
		smmu_mdma 282 Exynos4210
		fimd0 283
		mie0 284
		mdnie0 285 Exynos4412
		dsim0 286
		smmu_fimd0 287
		fimd1 288 Exynos4210
		mie1 289 Exynos4210
		dsim1 290 Exynos4210
		smmu_fimd1 291 Exynos4210
		pdma0 292
		pdma1 293
		pcie_phy 294
		sata_phy 295 Exynos4210
		tsi 296
		sdmmc0 297
		sdmmc1 298
		sdmmc2 299
		sdmmc3 300
		sdmmc4 301
		sata 302 Exynos4210
		sromc 303
		usb_host 304
		usb_device 305
		pcie 306
		onenand 307
		nfcon 308
		smmu_pcie 309
		gps 310
		smmu_gps 311
		uart0 312
		uart1 313
		uart2 314
		uart3 315
		uart4 316
		i2c0 317
		i2c1 318
		i2c2 319
		i2c3 320
		i2c4 321
		i2c5 322
		i2c6 323
		i2c7 324
		i2c_hdmi 325
		tsadc 326
		spi0 327
		spi1 328
		spi2 329
		i2s1 330
		i2s2 331
		pcm0 332
		i2s0 333
		pcm1 334
		pcm2 335
		pwm 336
		slimbus 337
		spdif 338
		ac97 339
		modemif 340
		chipid 341
		sysreg 342
		hdmi_cec 343
		mct 344
		wdt 345
		rtc 346
		keyif 347
		audss 348
		mipi_hsi 349 Exynos4210
		mdma2 350 Exynos4210
		pixelasyncm0 351
		pixelasyncm1 352
		fimc_lite0 353 Exynos4x12
		fimc_lite1 354 Exynos4x12
		ppmuispx 355 Exynos4x12
		ppmuispmx 356 Exynos4x12
		fimc_isp 357 Exynos4x12
		fimc_drc 358 Exynos4x12
		fimc_fd 359 Exynos4x12
		mcuisp 360 Exynos4x12
		gicisp 361 Exynos4x12
		smmu_isp 362 Exynos4x12
		smmu_drc 363 Exynos4x12
		smmu_fd 364 Exynos4x12
		smmu_lite0 365 Exynos4x12
		smmu_lite1 366 Exynos4x12
		mcuctl_isp 367 Exynos4x12
		mpwm_isp 368 Exynos4x12
		i2c0_isp 369 Exynos4x12
		i2c1_isp 370 Exynos4x12
		mtcadc_isp 371 Exynos4x12
		pwm_isp 372 Exynos4x12
		wdt_isp 373 Exynos4x12
		uart_isp 374 Exynos4x12
		asyncaxim 375 Exynos4x12
		smmu_ispcx 376 Exynos4x12
		spi0_isp 377 Exynos4x12
		spi1_isp 378 Exynos4x12
		pwm_isp_sclk 379 Exynos4x12
		spi0_isp_sclk 380 Exynos4x12
		spi1_isp_sclk 381 Exynos4x12
		uart_isp_sclk 382 Exynos4x12
		tmu_apbif 383

		[Mux Clocks]

		Clock ID SoC (if specific)
		-----------------------------------------------

		mout_fimc0 384
		mout_fimc1 385
		mout_fimc2 386
		mout_fimc3 387
		mout_cam0 388
		mout_cam1 389
		mout_csis0 390
		mout_csis1 391
		mout_g3d0 392
		mout_g3d1 393
		mout_g3d 394
		aclk400_mcuisp 395 Exynos4x12

		[Div Clocks]

		Clock ID SoC (if specific)
		-----------------------------------------------

		div_isp0 450 Exynos4x12
		div_isp1 451 Exynos4x12
		div_mcuisp0 452 Exynos4x12
		div_mcuisp1 453 Exynos4x12
		div_aclk200 454 Exynos4x12
		div_aclk400_mcuisp 455 Exynos4x12
		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume.

		All available clocks are defined as preprocessor macros in
		dt-bindings/clock/exynos4.h header and can be used in device
		tree sources.

		Example 1: An example of a clock controller node is listed below.

		@@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x100>;
		interrupts = <0 54 0>;
		clocks = <&clock 314>, <&clock 153>;
		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
		clock-names = "uart", "clk_uart_baud0";
		};

Documentation/devicetree/bindings/clock/exynos5250-clock.txt

+6 −157

Original line number	Diff line number	Diff line
		@@ -13,163 +13,12 @@ Required Properties:

		- #clock-cells: should be 1.

		The following is the list of clocks generated by the controller. Each clock is
		assigned an identifier and client nodes use this identifier to specify the
		clock which they consume.


		[Core Clocks]

		Clock ID
		----------------------------

		fin_pll 1

		[Clock Gate for Special Clocks]

		Clock ID
		----------------------------

		sclk_cam_bayer 128
		sclk_cam0 129
		sclk_cam1 130
		sclk_gscl_wa 131
		sclk_gscl_wb 132
		sclk_fimd1 133
		sclk_mipi1 134
		sclk_dp 135
		sclk_hdmi 136
		sclk_pixel 137
		sclk_audio0 138
		sclk_mmc0 139
		sclk_mmc1 140
		sclk_mmc2 141
		sclk_mmc3 142
		sclk_sata 143
		sclk_usb3 144
		sclk_jpeg 145
		sclk_uart0 146
		sclk_uart1 147
		sclk_uart2 148
		sclk_uart3 149
		sclk_pwm 150
		sclk_audio1 151
		sclk_audio2 152
		sclk_spdif 153
		sclk_spi0 154
		sclk_spi1 155
		sclk_spi2 156
		div_i2s1 157
		div_i2s2 158
		sclk_hdmiphy 159
		div_pcm0 160


		[Peripheral Clock Gates]

		Clock ID
		----------------------------

		gscl0 256
		gscl1 257
		gscl2 258
		gscl3 259
		gscl_wa 260
		gscl_wb 261
		smmu_gscl0 262
		smmu_gscl1 263
		smmu_gscl2 264
		smmu_gscl3 265
		mfc 266
		smmu_mfcl 267
		smmu_mfcr 268
		rotator 269
		jpeg 270
		mdma1 271
		smmu_rotator 272
		smmu_jpeg 273
		smmu_mdma1 274
		pdma0 275
		pdma1 276
		sata 277
		usbotg 278
		mipi_hsi 279
		sdmmc0 280
		sdmmc1 281
		sdmmc2 282
		sdmmc3 283
		sromc 284
		usb2 285
		usb3 286
		sata_phyctrl 287
		sata_phyi2c 288
		uart0 289
		uart1 290
		uart2 291
		uart3 292
		uart4 293
		i2c0 294
		i2c1 295
		i2c2 296
		i2c3 297
		i2c4 298
		i2c5 299
		i2c6 300
		i2c7 301
		i2c_hdmi 302
		adc 303
		spi0 304
		spi1 305
		spi2 306
		i2s1 307
		i2s2 308
		pcm1 309
		pcm2 310
		pwm 311
		spdif 312
		ac97 313
		hsi2c0 314
		hsi2c1 315
		hs12c2 316
		hs12c3 317
		chipid 318
		sysreg 319
		pmu 320
		cmu_top 321
		cmu_core 322
		cmu_mem 323
		tzpc0 324
		tzpc1 325
		tzpc2 326
		tzpc3 327
		tzpc4 328
		tzpc5 329
		tzpc6 330
		tzpc7 331
		tzpc8 332
		tzpc9 333
		hdmi_cec 334
		mct 335
		wdt 336
		rtc 337
		tmu 338
		fimd1 339
		mie1 340
		dsim0 341
		dp 342
		mixer 343
		hdmi 344
		g2d 345
		mdma0 346
		smmu_mdma0 347


		[Clock Muxes]

		Clock ID
		----------------------------
		mout_hdmi 1024
		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume.

		All available clocks are defined as preprocessor macros in
		dt-bindings/clock/exynos5250.h header and can be used in device
		tree sources.

		Example 1: An example of a clock controller node is listed below.

		@@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x100>;
		interrupts = <0 54 0>;
		clocks = <&clock 314>, <&clock 153>;
		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
		clock-names = "uart", "clk_uart_baud0";
		};

Documentation/devicetree/bindings/clock/exynos5420-clock.txt

+6 −178

Original line number	Diff line number	Diff line
		@@ -13,184 +13,12 @@ Required Properties:

		- #clock-cells: should be 1.

		The following is the list of clocks generated by the controller. Each clock is
		assigned an identifier and client nodes use this identifier to specify the
		clock which they consume.
		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume.


		[Core Clocks]

		Clock ID
		----------------------------

		fin_pll 1

		[Clock Gate for Special Clocks]

		Clock ID
		----------------------------
		sclk_uart0 128
		sclk_uart1 129
		sclk_uart2 130
		sclk_uart3 131
		sclk_mmc0 132
		sclk_mmc1 133
		sclk_mmc2 134
		sclk_spi0 135
		sclk_spi1 136
		sclk_spi2 137
		sclk_i2s1 138
		sclk_i2s2 139
		sclk_pcm1 140
		sclk_pcm2 141
		sclk_spdif 142
		sclk_hdmi 143
		sclk_pixel 144
		sclk_dp1 145
		sclk_mipi1 146
		sclk_fimd1 147
		sclk_maudio0 148
		sclk_maupcm0 149
		sclk_usbd300 150
		sclk_usbd301 151
		sclk_usbphy300 152
		sclk_usbphy301 153
		sclk_unipro 154
		sclk_pwm 155
		sclk_gscl_wa 156
		sclk_gscl_wb 157
		sclk_hdmiphy 158

		[Peripheral Clock Gates]

		Clock ID
		----------------------------

		aclk66_peric 256
		uart0 257
		uart1 258
		uart2 259
		uart3 260
		i2c0 261
		i2c1 262
		i2c2 263
		i2c3 264
		i2c4 265
		i2c5 266
		i2c6 267
		i2c7 268
		i2c_hdmi 269
		tsadc 270
		spi0 271
		spi1 272
		spi2 273
		keyif 274
		i2s1 275
		i2s2 276
		pcm1 277
		pcm2 278
		pwm 279
		spdif 280
		i2c8 281
		i2c9 282
		i2c10 283
		aclk66_psgen 300
		chipid 301
		sysreg 302
		tzpc0 303
		tzpc1 304
		tzpc2 305
		tzpc3 306
		tzpc4 307
		tzpc5 308
		tzpc6 309
		tzpc7 310
		tzpc8 311
		tzpc9 312
		hdmi_cec 313
		seckey 314
		mct 315
		wdt 316
		rtc 317
		tmu 318
		tmu_gpu 319
		pclk66_gpio 330
		aclk200_fsys2 350
		mmc0 351
		mmc1 352
		mmc2 353
		sromc 354
		ufs 355
		aclk200_fsys 360
		tsi 361
		pdma0 362
		pdma1 363
		rtic 364
		usbh20 365
		usbd300 366
		usbd301 377
		aclk400_mscl 380
		mscl0 381
		mscl1 382
		mscl2 383
		smmu_mscl0 384
		smmu_mscl1 385
		smmu_mscl2 386
		aclk333 400
		mfc 401
		smmu_mfcl 402
		smmu_mfcr 403
		aclk200_disp1 410
		dsim1 411
		dp1 412
		hdmi 413
		aclk300_disp1 420
		fimd1 421
		smmu_fimd1 422
		aclk166 430
		mixer 431
		aclk266 440
		rotator 441
		mdma1 442
		smmu_rotator 443
		smmu_mdma1 444
		aclk300_jpeg 450
		jpeg 451
		jpeg2 452
		smmu_jpeg 453
		aclk300_gscl 460
		smmu_gscl0 461
		smmu_gscl1 462
		gscl_wa 463
		gscl_wb 464
		gscl0 465
		gscl1 466
		clk_3aa 467
		aclk266_g2d 470
		sss 471
		slim_sss 472
		mdma0 473
		aclk333_g2d 480
		g2d 481
		aclk333_432_gscl 490
		smmu_3aa 491
		smmu_fimcl0 492
		smmu_fimcl1 493
		smmu_fimcl3 494
		fimc_lite3 495
		aclk_g3d 500
		g3d 501
		smmu_mixer 502

		Mux ID
		----------------------------

		mout_hdmi 640

		Divider ID
		----------------------------

		dout_pixel 768
		All available clocks are defined as preprocessor macros in
		dt-bindings/clock/exynos5420.h header and can be used in device
		tree sources.

		Example 1: An example of a clock controller node is listed below.

		@@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x100>;
		interrupts = <0 54 0>;
		clocks = <&clock 259>, <&clock 130>;
		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
		clock-names = "uart", "clk_uart_baud0";
		};

Documentation/devicetree/bindings/clock/exynos5440-clock.txt

+6 −39

Original line number	Diff line number	Diff line
		@@ -12,45 +12,12 @@ Required Properties:

		- #clock-cells: should be 1.

		The following is the list of clocks generated by the controller. Each clock is
		assigned an identifier and client nodes use this identifier to specify the
		clock which they consume.


		[Core Clocks]

		Clock ID
		----------------------------

		xtal 1
		arm_clk 2

		[Peripheral Clock Gates]

		Clock ID
		----------------------------

		spi_baud 16
		pb0_250 17
		pr0_250 18
		pr1_250 19
		b_250 20
		b_125 21
		b_200 22
		sata 23
		usb 24
		gmac0 25
		cs250 26
		pb0_250_o 27
		pr0_250_o 28
		pr1_250_o 29
		b_250_o 30
		b_125_o 31
		b_200_o 32
		sata_o 33
		usb_o 34
		gmac0_o 35
		cs250_o 36
		Each clock is assigned an identifier and client nodes can use this identifier
		to specify the clock which they consume.

		All available clocks are defined as preprocessor macros in
		dt-bindings/clock/exynos5440.h header and can be used in device
		tree sources.

		Example: An example of a clock controller node is listed below.

arch/arm/boot/dts/exynos4.dtsi

+37 −36

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@
		* published by the Free Software Foundation.
		*/

		#include <dt-bindings/clock/exynos4.h>
		#include "skeleton.dtsi"

		/ {
		@@ -119,7 +120,7 @@
		compatible = "samsung,exynos4210-fimc";
		reg = <0x11800000 0x1000>;
		interrupts = <0 84 0>;
		clocks = <&clock 256>, <&clock 128>;
		clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
		clock-names = "fimc", "sclk_fimc";
		samsung,power-domain = <&pd_cam>;
		samsung,sysreg = <&sys_reg>;
		@@ -130,7 +131,7 @@
		compatible = "samsung,exynos4210-fimc";
		reg = <0x11810000 0x1000>;
		interrupts = <0 85 0>;
		clocks = <&clock 257>, <&clock 129>;
		clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
		clock-names = "fimc", "sclk_fimc";
		samsung,power-domain = <&pd_cam>;
		samsung,sysreg = <&sys_reg>;
		@@ -141,7 +142,7 @@
		compatible = "samsung,exynos4210-fimc";
		reg = <0x11820000 0x1000>;
		interrupts = <0 86 0>;
		clocks = <&clock 258>, <&clock 130>;
		clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
		clock-names = "fimc", "sclk_fimc";
		samsung,power-domain = <&pd_cam>;
		samsung,sysreg = <&sys_reg>;
		@@ -152,7 +153,7 @@
		compatible = "samsung,exynos4210-fimc";
		reg = <0x11830000 0x1000>;
		interrupts = <0 87 0>;
		clocks = <&clock 259>, <&clock 131>;
		clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
		clock-names = "fimc", "sclk_fimc";
		samsung,power-domain = <&pd_cam>;
		samsung,sysreg = <&sys_reg>;
		@@ -163,7 +164,7 @@
		compatible = "samsung,exynos4210-csis";
		reg = <0x11880000 0x4000>;
		interrupts = <0 78 0>;
		clocks = <&clock 260>, <&clock 134>;
		clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
		clock-names = "csis", "sclk_csis";
		bus-width = <4>;
		samsung,power-domain = <&pd_cam>;
		@@ -178,7 +179,7 @@
		compatible = "samsung,exynos4210-csis";
		reg = <0x11890000 0x4000>;
		interrupts = <0 80 0>;
		clocks = <&clock 261>, <&clock 135>;
		clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
		clock-names = "csis", "sclk_csis";
		bus-width = <2>;
		samsung,power-domain = <&pd_cam>;
		@@ -194,7 +195,7 @@
		compatible = "samsung,s3c2410-wdt";
		reg = <0x10060000 0x100>;
		interrupts = <0 43 0>;
		clocks = <&clock 345>;
		clocks = <&clock CLK_WDT>;
		clock-names = "watchdog";
		status = "disabled";
		};
		@@ -203,7 +204,7 @@
		compatible = "samsung,s3c6410-rtc";
		reg = <0x10070000 0x100>;
		interrupts = <0 44 0>, <0 45 0>;
		clocks = <&clock 346>;
		clocks = <&clock CLK_RTC>;
		clock-names = "rtc";
		status = "disabled";
		};
		@@ -212,7 +213,7 @@
		compatible = "samsung,s5pv210-keypad";
		reg = <0x100A0000 0x100>;
		interrupts = <0 109 0>;
		clocks = <&clock 347>;
		clocks = <&clock CLK_KEYIF>;
		clock-names = "keypad";
		status = "disabled";
		};
		@@ -221,7 +222,7 @@
		compatible = "samsung,exynos4210-sdhci";
		reg = <0x12510000 0x100>;
		interrupts = <0 73 0>;
		clocks = <&clock 297>, <&clock 145>;
		clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
		clock-names = "hsmmc", "mmc_busclk.2";
		status = "disabled";
		};
		@@ -230,7 +231,7 @@
		compatible = "samsung,exynos4210-sdhci";
		reg = <0x12520000 0x100>;
		interrupts = <0 74 0>;
		clocks = <&clock 298>, <&clock 146>;
		clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
		clock-names = "hsmmc", "mmc_busclk.2";
		status = "disabled";
		};
		@@ -239,7 +240,7 @@
		compatible = "samsung,exynos4210-sdhci";
		reg = <0x12530000 0x100>;
		interrupts = <0 75 0>;
		clocks = <&clock 299>, <&clock 147>;
		clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
		clock-names = "hsmmc", "mmc_busclk.2";
		status = "disabled";
		};
		@@ -248,7 +249,7 @@
		compatible = "samsung,exynos4210-sdhci";
		reg = <0x12540000 0x100>;
		interrupts = <0 76 0>;
		clocks = <&clock 300>, <&clock 148>;
		clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
		clock-names = "hsmmc", "mmc_busclk.2";
		status = "disabled";
		};
		@@ -257,7 +258,7 @@
		compatible = "samsung,exynos4210-ehci";
		reg = <0x12580000 0x100>;
		interrupts = <0 70 0>;
		clocks = <&clock 304>;
		clocks = <&clock CLK_USB_HOST>;
		clock-names = "usbhost";
		status = "disabled";
		};
		@@ -266,7 +267,7 @@
		compatible = "samsung,exynos4210-ohci";
		reg = <0x12590000 0x100>;
		interrupts = <0 70 0>;
		clocks = <&clock 304>;
		clocks = <&clock CLK_USB_HOST>;
		clock-names = "usbhost";
		status = "disabled";
		};
		@@ -276,7 +277,7 @@
		reg = <0x13400000 0x10000>;
		interrupts = <0 94 0>;
		samsung,power-domain = <&pd_mfc>;
		clocks = <&clock 273>;
		clocks = <&clock CLK_MFC>;
		clock-names = "mfc";
		status = "disabled";
		};
		@@ -285,7 +286,7 @@
		compatible = "samsung,exynos4210-uart";
		reg = <0x13800000 0x100>;
		interrupts = <0 52 0>;
		clocks = <&clock 312>, <&clock 151>;
		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
		clock-names = "uart", "clk_uart_baud0";
		status = "disabled";
		};
		@@ -294,7 +295,7 @@
		compatible = "samsung,exynos4210-uart";
		reg = <0x13810000 0x100>;
		interrupts = <0 53 0>;
		clocks = <&clock 313>, <&clock 152>;
		clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
		clock-names = "uart", "clk_uart_baud0";
		status = "disabled";
		};
		@@ -303,7 +304,7 @@
		compatible = "samsung,exynos4210-uart";
		reg = <0x13820000 0x100>;
		interrupts = <0 54 0>;
		clocks = <&clock 314>, <&clock 153>;
		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
		clock-names = "uart", "clk_uart_baud0";
		status = "disabled";
		};
		@@ -312,7 +313,7 @@
		compatible = "samsung,exynos4210-uart";
		reg = <0x13830000 0x100>;
		interrupts = <0 55 0>;
		clocks = <&clock 315>, <&clock 154>;
		clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
		clock-names = "uart", "clk_uart_baud0";
		status = "disabled";
		};
		@@ -323,7 +324,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x13860000 0x100>;
		interrupts = <0 58 0>;
		clocks = <&clock 317>;
		clocks = <&clock CLK_I2C0>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_bus>;
		@@ -336,7 +337,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x13870000 0x100>;
		interrupts = <0 59 0>;
		clocks = <&clock 318>;
		clocks = <&clock CLK_I2C1>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_bus>;
		@@ -349,7 +350,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x13880000 0x100>;
		interrupts = <0 60 0>;
		clocks = <&clock 319>;
		clocks = <&clock CLK_I2C2>;
		clock-names = "i2c";
		status = "disabled";
		};
		@@ -360,7 +361,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x13890000 0x100>;
		interrupts = <0 61 0>;
		clocks = <&clock 320>;
		clocks = <&clock CLK_I2C3>;
		clock-names = "i2c";
		status = "disabled";
		};
		@@ -371,7 +372,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x138A0000 0x100>;
		interrupts = <0 62 0>;
		clocks = <&clock 321>;
		clocks = <&clock CLK_I2C4>;
		clock-names = "i2c";
		status = "disabled";
		};
		@@ -382,7 +383,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x138B0000 0x100>;
		interrupts = <0 63 0>;
		clocks = <&clock 322>;
		clocks = <&clock CLK_I2C5>;
		clock-names = "i2c";
		status = "disabled";
		};
		@@ -393,7 +394,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x138C0000 0x100>;
		interrupts = <0 64 0>;
		clocks = <&clock 323>;
		clocks = <&clock CLK_I2C6>;
		clock-names = "i2c";
		status = "disabled";
		};
		@@ -404,7 +405,7 @@
		compatible = "samsung,s3c2440-i2c";
		reg = <0x138D0000 0x100>;
		interrupts = <0 65 0>;
		clocks = <&clock 324>;
		clocks = <&clock CLK_I2C7>;
		clock-names = "i2c";
		status = "disabled";
		};
		@@ -417,7 +418,7 @@
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock 327>, <&clock 159>;
		clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
		clock-names = "spi", "spi_busclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&spi0_bus>;
		@@ -432,7 +433,7 @@
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock 328>, <&clock 160>;
		clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
		clock-names = "spi", "spi_busclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&spi1_bus>;
		@@ -447,7 +448,7 @@
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock 329>, <&clock 161>;
		clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
		clock-names = "spi", "spi_busclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&spi2_bus>;
		@@ -458,7 +459,7 @@
		compatible = "samsung,exynos4210-pwm";
		reg = <0x139D0000 0x1000>;
		interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
		clocks = <&clock 336>;
		clocks = <&clock CLK_PWM>;
		clock-names = "timers";
		#pwm-cells = <2>;
		status = "disabled";
		@@ -475,7 +476,7 @@
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x12680000 0x1000>;
		interrupts = <0 35 0>;
		clocks = <&clock 292>;
		clocks = <&clock CLK_PDMA0>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		#dma-channels = <8>;
		@@ -486,7 +487,7 @@
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x12690000 0x1000>;
		interrupts = <0 36 0>;
		clocks = <&clock 293>;
		clocks = <&clock CLK_PDMA1>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		#dma-channels = <8>;
		@@ -497,7 +498,7 @@
		compatible = "arm,pl330", "arm,primecell";
		reg = <0x12850000 0x1000>;
		interrupts = <0 34 0>;
		clocks = <&clock 279>;
		clocks = <&clock CLK_MDMA>;
		clock-names = "apb_pclk";
		#dma-cells = <1>;
		#dma-channels = <8>;
		@@ -511,7 +512,7 @@
		reg = <0x11c00000 0x20000>;
		interrupt-names = "fifo", "vsync", "lcd_sys";
		interrupts = <11 0>, <11 1>, <11 2>;
		clocks = <&clock 140>, <&clock 283>;
		clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
		clock-names = "sclk_fimd", "fimd";
		samsung,power-domain = <&pd_lcd0>;
		status = "disabled";

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