drivers: spi_xlnx_axi_quadspi: add STARTUP block workaround support

Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.

See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US



Signed-off-by: Robert Hancock <robert.hancock@calian.com>