soc/intel_adsp: Simplify boot SRAM initialization

The module copy was clearing BSS sections from the module list, but we
already clear the full memory space immediately after SRAM power-up so
that's needless, just like the legacy reset vector bss clear that got
removed earlier.  (Yes: that means that this code used to be writing
zeros to .bss three times!)

Similarly, put a symmetric clear on the LP-SRAM bank for safety (it's
not currently used by Zephyr but we do start it up).  And move the
cache flush to the end of initialization immediately before OS
handoff.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>