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Commit b6122c35 authored by Jimmy Zheng's avatar Jimmy Zheng Committed by Fabio Baltieri
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soc: riscv: andes_v5: add Andes I/O Coherence Port option



Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle
cache coherency between cache and external non-caching master, such as DMA
controller.

Signed-off-by: default avatarJimmy Zheng <jimmyzhe@andestech.com>
parent a1665cbf
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