drivers: flash: nrf_qspi_nor: Fix setting of the base clock divider

On nRF53 Series SoCs, the highest SCK frequencies can only be achieved
when the HFCLK192M clock divider is changed from the default /4 setting.
Such change results in increased power consumption, so the divider needs
to be changed only for periods when it is actually necessary.
This commit modifies the driver behavior so that it changes the divider
only when a QSPI bus operation is performed.
However, when XIP accesses to the flash chip are also used, it may be
needed to keep the divider changed even when the driver is idle so that
the XIP access speed is not reduced, hence a custom API function that
allows forcing this is introduced for the driver.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>