drivers: sensor: stm32_vref: update incorrect comment

The ICACHE must be disabled on STM32H5 series due to documented
behaviour of the flash controller, not to an errata.

For a more technical explaination: (see RM0492 for references)
 -  on STM32H5, the ICACHE block is interposed on C-bus between
    the Cortex-M33 and the FLASH (§2.1.1)
 -  the ICACHE determines if accesses are cacheable or non-cacheable
    based on an AHB attribute; the Cortex-M33 sets this attribute or
    not depending on the MPU configuration (§8.4.6)
 -  when a cacheable access is requested by the Cortex-M33, if the
    requested data is not present in ICACHE (cache miss), a cache line
    refill (128-bit burst read) is performed (§8.4.7)
 -  however, all accesses to OTP and Read-Only regions of the FLASH must
    be done with caching disabled (§7.3.2); indeed, the accesses MUST be
    16 or 32-bit sized - otherwise, the flash interface raises a bus
    error (§7.5.9 / Table 38 "OTP/RO access constraints").

    This is the behaviour that was observed and lead to the introduction
    of ICACHE disable code in 065a8f25.

Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>