dt-bindings: fix MDC clock divider bindings for Xilinx GEM

The original implementation of the GEM's device tree binding
implied that:
1) on the UltraScale+, the MDC clock divider is applied to
the LPD_LSBUS_CLK. According to the most recent documentation,
this is not the case, instead, the MDC divider is applied to
the IOU_SWITCH_CLK.
2) any MDC divider greater than 32 is reserved to the Zynq-7000
(in the driver itself, accessibility of the larger dividers was
also #ifdef'd), as the Zynq's MDC clock source, the cpu_1x
clock, can have significantly higher frequencies than the
UltraScale's LPD_LSBUS clock.

The respective documentation in the device tree binding header
file is hereby fixed.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>