soc/intel_adsp: Add full cache enable logic

Earlier platforms were relying on the system ROM to have done this
correctly, but with CAVS 2.5 we launch the CPU into our own code
directly.  So we need to do those steps manually.  And there's also a
new one on this hardware, which has software power control over the
cache SRAM.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>