soc/intel_adsp: Fix ATOMCTL on MP startup

Hardware defaults for the secondary CPUs have the S32C1I instruction
set to be atomic only with respect to the local L1 cache, which is
basically useless on a multiprocessor platform.  The CPU0 boot path
sets this manually, so we need to duplicate that here.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>