soc: riscv: gd32vf103: simplify MCAUSE exception mask handling

The exception mask needs to cover MCAUSE bits 11:0, there's no need to
overengineer this setting using DT properties.

Ref. https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mcause



Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>