dts: xtensa: intel: Reorder power domains by bit position in ACE30

Rearrange the power domain entries in the ACE30 PTL device tree source
file to be in ascending order according to their bit positions. This
reordering improves the readability of the device tree source by
grouping power domains logically according to their bit position within
the power management registers.

The changes in this patch include:
- Moving 'ml1_domain' and 'ml0_domain' to their correct positions
  according to their bit-position values (13 and 12, respectively).
- Adjusting the order of 'io3_domain', 'io2_domain', 'io1_domain', and
  'io0_domain' to reflect their bit positions (11, 10, 9, and 8).
- Placing 'hub_hp_domain' and 'hst_domain' at their new positions
  according to their bit-position values (6 and 5).

No functional changes are introduced with this patch. It solely aims to
make the device tree source more intuitive and easier to navigate when
mapping power domains to their respective control bits.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>