intel_adsp: ace30: Correct power control register bitfield definitions

This patch updates the power control and status register bitfield
definitions in the ACE30 PTL ADSP power management header to match the
documented hardware specifications. The previous definitions contained
discrepancies that did not align with the actual hardware layout,
potentially leading to incorrect assumptions and usage within the
firmware.

Changes made in this patch:
- Renamed 'rsvd0' to 'rsvd4' to accurately represent the reserved bits
  starting at bit position 4.
- Removed the 'rsvd6' field, which was incorrectly defined and is not
  present in the hardware register layout.
- Adjusted the bit widths for 'ioxpgs' and 'mlpgs' to correctly reflect
  the number of bits these fields occupy in the hardware.
- Introduced a new 'rsvd15' field in both 'ace_pwrctl2' and
  'ace_pwrsts2' structures to account for the remaining reserved bits,
  ensuring the structure sizes accurately represent the full register
  width.

By correcting these bitfield definitions, the firmware's power
management code will now be consistent with the actual hardware design,
improving reliability and maintainability of the codebase.

Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>