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Commit 3abb0c9b authored by Erwan Gouriou's avatar Erwan Gouriou Committed by Carles Cufí
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drivers: clock_control: stm32f3: Enable PWR clock to access BDCR 



BDCR could be required for LSE or RTC for instance.
Enable it here as for now, no sophisticated PM handling is available
on F3 series.

Signed-off-by: default avatarErwan Gouriou <erwan.gouriou@linaro.org>
parent bd9bd38b
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