soc: adi: max32: Enable primary core to configure/start secondary core

Adds support for the primary m4 core to configure the boot address and
start the clock for the secondary risc-v core. Unlike the msdk which
defers this function to applications and requires users to copy/paste
code from an msdk example application into their own application, in
zephyr it is implemented in the common soc init routine of the primary
core. It can be enabled/disabled and configured with Kconfig symbols and
a devicetree chosen node, allowing applications to override board-level
defaults if desired using overlays instead of modifying zephyr code.

Signed-off-by: Maureen Helm <maureen.helm@analog.com>