board: olimex_stm32_e407: fix default 48MHz clock divisor

The previously used default value of 4 for the PPL_Q_DIVISOR results
in a frequency of 84MHz which is outside the acceptable range
of 47.88MHz to 48.12MHz.

The new value of 7 results in exactly 48MHz.

Signed-off-by: Erwin Rol <erwin@erwinrol.com>